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  • only in /netgear-R7000-V1.0.7.12_1.2.5/src/shared/

Lines Matching refs:max_mask

77 	uint32 *max_mask, uint32 *clk_ctl_st);
80 uint32 max_mask, uint32 clk_ctl_st);
2228 uint32 min_mask = 0, max_mask = 0;
2243 max_mask = 0xfffff;
2247 max_mask = 0xfffff;
2263 max_mask = ~(~0 << rsrcs);
2269 * max_mask = 0x7fff;
2288 max_mask = 0x1ff;
2313 max_mask = 0x1ff;
2330 max_mask = (1<<3) | min_mask | PMURES_BIT(RES43602_RADIO_PU) |
2343 max_mask = PMURES_BIT(RES43143_EXT_SWITCHER_PWM) | PMURES_BIT(RES43143_XTAL_PU) |
2363 max_mask = 0x3ff63e;
2372 max_mask = ~(~0 << rsrcs);
2394 max_mask = ~(~0 << rsrcs);
2403 max_mask = 0x1ffffff;
2412 max_mask = 0xfffffff;
2421 max_mask = 0xffff;
2429 max_mask = 0x7FFFFFFF;
2442 max_mask = 0x7FFFFFFF;
2469 max_mask = 0x7FFFFFFF;
2516 max_mask = 0x7FFFFFFF;
2525 max_mask = (1 << rsrcs) - 1;
2559 max_mask = 0x3FFFFFFF;
2579 max_mask = 0x3FFFFFFF;
2588 max_mask = 0x7FFFFFFF;
2597 max_mask = 0x7FFFFFFF;
2611 PMU_MSG(("Applying rmax=%d to max_mask\n", sii->nvram_max_mask));
2612 max_mask = sii->nvram_max_mask;
2616 *pmax = max_mask;
2685 uint32 min_mask = 0, max_mask = 0;
2999 si_pmu_res_masks(sih, &min_mask, &max_mask);
3004 /* It is required to program max_mask first and then min_mask */
3008 max_mask |= R_REG(osh, PMUREG(sih, max_res_mask));
3016 max_mask = (uint32)bcm_strtoul(val, NULL, 0);
3068 if (max_mask) {
3069 /* Ensure there is no bit set in min_mask which is not set in max_mask */
3070 max_mask |= min_mask;
3078 OR_REG(osh, PMUREG(sih, max_res_mask), max_mask);
3097 if (max_mask) {
3098 PMU_MSG(("Changing max_res_mask to 0x%x\n", max_mask));
3099 W_REG(osh, PMUREG(sih, max_res_mask), max_mask);
4732 uint32 *max_mask, uint32 *clk_ctl_st)
4738 *max_mask = R_REG(osh, PMUREG(sih, max_res_mask));
4777 uint32 *max_mask, uint32 *clk_ctl_st)
4789 *max_mask = R_REG(osh, PMUREG(sih, max_res_mask));
4940 uint32 min_mask = 0, max_mask = 0, clk_ctl_st = 0;
4967 si_pmu_pll_off(sih, osh, cc, &min_mask, &max_mask, &clk_ctl_st);
4979 si_pmu_pll_on(sih, osh, cc, min_mask, max_mask, clk_ctl_st);
5154 uint32 min_mask = 0, max_mask = 0, clk_ctl_st = 0;
5182 si_pmu_pll_off(sih, osh, cc, &min_mask, &max_mask, &clk_ctl_st);
5197 si_pmu_pll_on(sih, osh, cc, min_mask, max_mask, clk_ctl_st);
6786 uint32 max_mask = 0;
6804 si_pmu_res_masks(sih, &min_mask, &max_mask);
8706 uint32 min_mask = 0, max_mask = 0;
8730 si_pmu_res_masks(sih, &min_mask, &max_mask);
8731 max_mask = 0; /* Only care about min_mask for now */
8750 if (max_mask) {
8752 max_mask |= si_pmu_res_deps(sih, osh, cc, max_mask, FALSE);
8753 W_REG(osh, PMUREG(sih, max_res_mask), max_mask);