Lines Matching refs:fvco
3129 /* the following table is based on 880Mhz fvco */
3369 /* the following table is based on 880Mhz fvco */
3408 /* the following table is based on 1760Mhz fvco */
3445 /* the following table is based on 1440Mhz fvco */
3913 /** returns chip specific default pll fvco frequency in [khz] units */
4193 uint32 fvco = si_pmu1_pllfvco0(sih); /* in [khz] */
4224 ndiv_int = (fvco * p1div) / xtal;
4226 /* ndiv_frac = (uint32) (((uint64) (fvco * p1div - xtal * ndiv_int) * (1 << 24)) / xtal) */
4227 bcm_uint64_multiple_add(&temp_high, &temp_low, fvco * p1div - xtal * ndiv_int, 1 << 24, 0);
4240 fvco = FVCO_960; /* USB/HSIC FVCO is always 960 MHz, regardless of BB FVCO */
4242 ((((uint32) fvco << 12) / xtal) & 0x000FFFFF);
4244 ndiv_int = (fvco * p1div) / xtal;
4247 * ndiv_frac = (uint32) (((uint64) (fvco * p1div - xtal * ndiv_int) * (1 << 20)) /
4250 bcm_uint64_multiple_add(&temp_high, &temp_low, fvco * p1div - xtal * ndiv_int, 1 << 20, 0);
5601 si_pmu_fvco_pllreg(si_t *sih, uint32 *fvco, uint32 *pllreg)
5606 if (fvco)
5607 *fvco = si_pmu1_pllfvco0(sih)/1000;
7727 uint32 xf, ndiv_int, ndiv_frac, fvco, pll_reg, p1_div_scale;
7776 bcm_uint64_right_shift(&fvco, r_high, r_low, P1_DIV_SCALE_BITS);
7780 return fvco;