Lines Matching refs:PMU_MSG
54 #define PMU_MSG(args)
2606 PMU_MSG(("Applying rmin=%d to min_mask\n", sii->nvram_min_mask));
2611 PMU_MSG(("Applying rmax=%d to max_mask\n", sii->nvram_max_mask));
2644 PMU_MSG(("Changing rsrc %d res_dep_mask to 0x%x\n", i,
2650 PMU_MSG(("Adding 0x%x to rsrc %d res_dep_mask\n",
2656 PMU_MSG(("Removing 0x%x from rsrc %d res_dep_mask\n",
2937 PMU_MSG(("Changing rsrc %d res_updn_timer to 0x%x\n",
2960 PMU_MSG(("Applying %s=%s to rsrc %d res_updn_timer\n", name, val, i));
2973 PMU_MSG(("Applying %s=%s to rsrc %d res_dep_mask\n", name, val, i));
3015 PMU_MSG(("Applying brmax=%s to max_res_mask\n", val));
3021 PMU_MSG(("Applying brmin=%s to min_res_mask\n", val));
3092 PMU_MSG(("Changing min_res_mask to 0x%x\n", min_mask));
3098 PMU_MSG(("Changing max_res_mask to 0x%x\n", max_mask));
3219 PMU_MSG(("XTAL %d.%d MHz (%d)\n", xtal / 1000, xtal % 1000, xt->xf));
3225 PMU_MSG(("PLL already programmed for %d.%d MHz\n",
3235 PMU_MSG(("Reprogramming PLL for %d.%d MHz (was %d.%dMHz)\n",
3239 PMU_MSG(("Programming PLL for %d.%d MHz\n",
3259 PMU_MSG(("Done masking\n"));
3292 PMU_MSG(("Done pll\n"));
3840 PMU_MSG(("si_pmu1_xtaltab0: Unknown chipid %s\n", bcm_chipname(sih->chip, chn, 8)));
3906 PMU_MSG(("si_pmu1_xtaldef0: Unknown chipid %s\n", bcm_chipname(sih->chip, chn, 8)));
3967 PMU_MSG(("si_pmu1_pllfvco0: Unknown chipid %s\n", bcm_chipname(sih->chip, chn, 8)));
4260 PMU_MSG(("xtal PLLCTRL0 PLLCTRL1 PLLCTRL2 PLLCTRL3"));
4261 PMU_MSG((" PLLCTRL4 PLLCTRL5 PLLCTRL6 PLLCTRL7\n"));
4262 PMU_MSG(("%d ", xtal));
4264 PMU_MSG((" 0x%08X", PLL_control[i]));
4268 PMU_MSG(("\n"));
4546 PMU_MSG(("XTAL %d.%d MHz (%d)\n", xtal / 1000, xtal % 1000, xt->xf));
4547 PMU_MSG(("Programming PLL for %d.%d MHz\n", xt->fref / 1000, xt->fref % 1000));
4570 PMU_MSG(("Adjusting PLL buffer drive strength: %x\n", buf_strength));
4995 PMU_MSG(("Unspecified xtal frequency, skip PLL configuration\n"));
5005 PMU_MSG(("Unsupported xtal frequency %d.%d MHz, skip PLL configuration\n",
5015 PMU_MSG(("PLL already programmed for %d.%d MHz\n",
5020 PMU_MSG(("XTAL %d.%d MHz (%d)\n", xtal / 1000, xtal % 1000, xt->xf));
5021 PMU_MSG(("Programming PLL for %d.%d MHz\n", xt->fref / 1000, xt->fref % 1000));
5218 PMU_MSG(("Unspecified xtal frequency, skip PLL configuration\n"));
5231 PMU_MSG(("Unsupported xtal frequency %d.%d MHz, skip PLL configuration\n",
5242 PMU_MSG(("PLL already programmed for %d.%d MHz\n",
5247 PMU_MSG(("XTAL %d.%d MHz (%d)\n", xtal / 1000, xtal % 1000, xt->xf));
5248 PMU_MSG(("Programming PLL for %d.%d MHz\n", xt->fref / 1000, xt->fref % 1000));
5354 PMU_MSG(("Done masking\n"));
5407 PMU_MSG(("Adjusting PLL buffer drive strength: %x\n", buf_strength));
5415 PMU_MSG(("Done pll\n"));
5551 PMU_MSG(("si_pmu1_cpuclk0: Unknown chipid %s\n", bcm_chipname(sih->chip, chn, 8)));
5587 PMU_MSG(("si_mac_clk: Unknown chipid %s\n", bcm_chipname(sih->chip, chn, 8)));
5631 PMU_MSG(("si_mac_clk: Unknown chipid %s\n", bcm_chipname(sih->chip, chn, 8)));
5705 PMU_MSG(("HTAVAIL is set, so not updating BBPLL Frequency \n"));
5977 PMU_MSG(("No PLL init done for chip %s rev %d pmurev %d\n",
6095 PMU_MSG(("No ALP clock specified "
6315 PMU_MSG(("No backplane clock specified "
6695 PMU_MSG(("No SDIO Drive strength init done for chip %s rev %d pmurev %d\n",
6722 PMU_MSG(("SDIO: %dmA drive strength requested; set to %dmA\n",
6821 PMU_MSG(("si_pmu_res_uptime: rsrc %u uptime %u(deps 0x%08x uptime %u)\n",
6861 PMU_MSG(("si_pmu_otp_power: OTP is disabled\n"));
6944 PMU_MSG(("Adding rsrc 0x%x to min_res_mask\n", min_mask));
6970 PMU_MSG(("Removing rsrc 0x%x from min_res_mask\n", min_mask));
6979 PMU_MSG(("OTP ready bit not %s after wait\n", (on_check ? "ON" : "OFF")));
7036 PMU_MSG(("RCal completed, status 0x%x, code 0x%x\n",
7089 PMU_MSG(("RCal completed, status 0x%x, code 0x%x\n",