Lines Matching defs:spuravoid
103 static void si_pmu_spuravoid_pllupdate(si_t *sih, chipcregs_t *cc, osl_t *osh, uint8 spuravoid);
7132 si_pmu_spuravoid(si_t *sih, osl_t *osh, uint8 spuravoid)
7145 /* spuravoid is not ready for 43242 */
7176 si_pmu_spuravoid_pllupdate(sih, cc, osh, spuravoid);
7190 uint32 max_res_mask, uint32 clk_ctl_st, uint8 spuravoid)
7203 /* spuravoid is not ready for 43242 */
7230 si_pmu_spuravoid_pllupdate(sih, cc, osh, spuravoid);
7242 /* For having the pllcontrol data values for spuravoid */
7275 si_pmu_pllctrl_spurupdate(si_t *sih, osl_t *osh, chipcregs_t *cc, uint8 spuravoid,
7280 if (pllctrl_spur[indx].spuravoid_mode == spuravoid) {
7288 si_pmu_spuravoid_pllupdate(si_t *sih, chipcregs_t *cc, osl_t *osh, uint8 spuravoid)
7302 if (spuravoid > 2)
7303 spuravoid = 0;
7305 si_pmu_pllctrl_spurupdate(sih, osh, cc, spuravoid, spuravoid_4324,
7320 if (spuravoid == 1) {
7358 if (spuravoid > 2)
7359 spuravoid = 0;
7365 tmp |= (bcm5357_bcm43236_p1div[spuravoid] << PMU1_PLL0_PC0_P1DIV_SHIFT);
7372 tmp |= (bcm5357_bcm43236_ndiv[spuravoid]) << PMU1_PLL0_PC2_NDIV_INT_SHIFT;
7382 if (spuravoid == 2) {
7385 } else if (spuravoid == 1) {
7393 if (spuravoid == 2) {
7398 } else if (spuravoid == 1) {
7415 if (spuravoid == 1) {
7447 if (spuravoid == 1) {
7481 if (spuravoid == 1) {
7523 if (spuravoid == 1) { /* spur_avoid ON, enable 41/82/164Mhz clock mode */
7541 if (spuravoid == 1) { /* spur_avoid ON, enable 41/82/164Mhz clock mode */
7575 if (spuravoid == 1)
7602 if (spuravoid == 1) {
7640 xt = (spuravoid == 1) ? pmu2_xtaltab0_adfll_492 : pmu2_xtaltab0_adfll_485;
7671 switch (spuravoid) {
7711 /* TODO - set PLLCTL registers (via set_PLL_control_regs), based on spuravoid */