Lines Matching defs:pllctrlreg_update
4123 * 'pllctrlreg_update': contains info on what entries to use in 'pllctrlreg_val' for the given
4132 uint8 spur_mode, const pllctrl_data_t *pllctrlreg_update, uint32 array_size,
4138 ASSERT(pllctrlreg_update);
4149 if (!((pllctrlreg_update[indx].clock == (uint16)xtal) &&
4150 (pllctrlreg_update[indx].mode == spur_mode)))
4163 xf = pllctrlreg_update[indx].xf;
4303 const pllctrl_data_t *pllctrlreg_update = NULL;
4344 pllctrlreg_update = pmu1_xtaltab0_4335;
4348 pllctrlreg_update = pmu1_xtaltab0_4335_drv;
4372 pllctrlreg_update = pmu1_xtaltab0_4345;
4393 pllctrlreg_update = pmu1_xtaltab0_4350;
4425 pllctrlreg_update = pmu1_xtaltab0_43242;
4456 if (!update_required && pllctrlreg_update) {
4461 xf = si_pmu_pllctrlreg_update(sih, osh, NULL, xtal, 0, pllctrlreg_update,
4486 si_pmu_pllctrlreg_update(sih, osh, cc, xtal, 0, pllctrlreg_update, array_size,