Lines Matching defs:p1div
3343 uint8 p1div;
3518 /* fref xf p1div p2div ndiv_int ndiv_frac */
4197 uint8 p1div;
4222 /* xtal and FVCO are in kHz. xtal/p1div must be <= 50MHz */
4223 p1div = 1 + (uint8) ((xtal * 1000) / 50000000UL);
4224 ndiv_int = (fvco * p1div) / xtal;
4226 /* ndiv_frac = (uint32) (((uint64) (fvco * p1div - xtal * ndiv_int) * (1 << 24)) / xtal) */
4227 bcm_uint64_multiple_add(&temp_high, &temp_low, fvco * p1div - xtal * ndiv_int, 1 << 24, 0);
4234 (p1div << 16) | (ndiv_mode << 20) | (ndiv_int << 23);
4244 ndiv_int = (fvco * p1div) / xtal;
4247 * ndiv_frac = (uint32) (((uint64) (fvco * p1div - xtal * ndiv_int) * (1 << 20)) /
4250 bcm_uint64_multiple_add(&temp_high, &temp_low, fvco * p1div - xtal * ndiv_int, 1 << 20, 0);
4254 PLL_control[6] = (PLL_4345_CONTROL6_DEFAULT & 0xFFFFE000) | p1div | (ndiv_int << 3);
4549 /* Write p1div and p2div to pllcontrol[0] */
4550 tmp = ((xt->p1div << PMU1_PLL0_PC0_P1DIV_SHIFT) & PMU1_PLL0_PC0_P1DIV_MASK) |
5356 /* Write p1div and p2div to pllcontrol[0] */
5360 tmp |= ((xt->p1div << PMU1_PLL0_PC0_P1DIV_SHIFT) & PMU1_PLL0_PC0_P1DIV_MASK) |
5686 uint32 vcofreq_withfrac, p1div, ndiv_int, fraca, ndiv_mode, reg;
5728 p1div = 0x1;
5736 (p1div << p1div_shift);
5760 p1div; /* predivider: divides x-tal freq */
5773 p1div = 1; /* do not divide x-tal frequency */
5782 p1div = (reg >> 16) & 0xf;
5792 xtal1 = 10000 * xtalfreq / p1div; /* in [100Hz] units */
6165 uint32 w, ndiv, p1div, p2div;
6178 p1div = (w & PMU6_4706_PROC_P1DIV_MASK) >> PMU6_4706_PROC_P1DIV_SHIFT;
6183 clock = (25000000 / 4) * ndiv * p2div / p1div;
6186 clock = (25000000 / 2) * ndiv * p2div / p1div;
7569 p1_div = params_tbl->p1div;