Lines Matching defs:min_mask
76 static void si_pmu_pll_off(si_t *sih, osl_t *osh, chipcregs_t *cc, uint32 *min_mask,
79 static void si_pmu_pll_on(si_t *sih, osl_t *osh, chipcregs_t *cc, uint32 min_mask,
2228 uint32 min_mask = 0, max_mask = 0;
2239 min_mask = PMURES_BIT(RES4328_EXT_SWITCHER_PWM) |
2253 min_mask |= PMURES_BIT(RES4325B0_CBUCK_LPOM);
2256 min_mask |= PMURES_BIT(RES4325B0_CLDO_PU);
2258 min_mask |= PMURES_BIT(RES4325_OTP_PU);
2261 min_mask |= PMURES_BIT(RES4325_BUCK_BOOST_BURST);
2266 /* default min_mask = 0x80000cbb is wrong */
2267 min_mask = 0xcbb;
2279 min_mask = PMURES_BIT(RES4322_RF_LDO) |
2283 min_mask += PMURES_BIT(RES4322_SI_PLL_ON) |
2305 min_mask = 0x103;
2320 min_mask = PMURES_BIT(RES43602_LPLDO_PU) | PMURES_BIT(RES43602_REGULATOR) |
2330 max_mask = (1<<3) | min_mask | PMURES_BIT(RES43602_RADIO_PU) |
2335 /* min_mask is updated after SR code is downloaded to txfifo */
2337 min_mask = PMURES_BIT(RES43602_LPLDO_PU);
2355 min_mask = PMURES_BIT(RES4329_CBUCK_LPOM) |
2358 min_mask = PMURES_BIT(RES4329_CBUCK_LPOM) | PMURES_BIT(RES4329_CLDO_PU);
2361 min_mask |= PMURES_BIT(RES4329_OTP_PU);
2369 min_mask = PMURES_BIT(RES4315_CBUCK_LPOM);
2370 min_mask |= PMURES_BIT(RES4315_CLDO_PU);
2377 min_mask = PMURES_BIT(RES4319_CBUCK_LPOM) |
2389 min_mask = PMURES_BIT(RES4319_CBUCK_LPOM) |
2399 min_mask = PMURES_BIT(RES4336_CBUCK_LPOM) | PMURES_BIT(RES4336_CLDO_PU) |
2408 min_mask = PMURES_BIT(RES4330_CBUCK_LPOM) | PMURES_BIT(RES4330_CLDO_PU) |
2416 min_mask = PMURES_BIT(RES4313_BB_PU_RSRC) |
2427 min_mask = pmu_corereg(sih, SI_CC_IDX, min_res_mask, 0, 0);
2433 min_mask = pmu_corereg(sih, SI_CC_IDX, min_res_mask, 0, 0);
2447 min_mask = PMURES_BIT(RES4345_LPLDO_PU) |
2464 /* min_mask is updated after SR code is downloaded to txfifo */
2466 min_mask = PMURES_BIT(RES4345_LPLDO_PU);
2486 min_mask = PMURES_BIT(RES4350_LPLDO_PU) |
2490 min_mask = 0xfc22f77;
2495 min_mask = pmu_corereg(sih, SI_CC_IDX,
2502 /* min_mask is updated after SR code is downloaded to txfifo */
2504 min_mask = PMURES_BIT(RES4350_LPLDO_PU);
2508 min_mask = PMURES_BIT(RES4350_LDO3P3_PU) |
2522 min_mask = pmu_corereg(sih, SI_CC_IDX, min_res_mask, 0, 0);
2533 min_mask = PMURES_BIT(RES4314_LPLDO_PU) |
2541 min_mask = PMURES_BIT(RES4314_LPLDO_PU) |
2563 min_mask = PMURES_BIT(RES4314_LPLDO_PU) |
2584 min_mask = PMURES_BIT(RES4334_LPLDO_PU) | PMURES_BIT(RES4334_RESET_PULLDN_DIS) |
2593 min_mask = PMURES_BIT(RES4334_LPLDO_PU);
2606 PMU_MSG(("Applying rmin=%d to min_mask\n", sii->nvram_min_mask));
2607 min_mask = sii->nvram_min_mask;
2615 *pmin = min_mask;
2685 uint32 min_mask = 0, max_mask = 0;
2999 si_pmu_res_masks(sih, &min_mask, &max_mask);
3002 min_mask |= si_pmu_res_deps(sih, osh, cc, min_mask, FALSE);
3004 /* It is required to program max_mask first and then min_mask */
3007 min_mask |= R_REG(osh, PMUREG(sih, min_res_mask));
3022 min_mask = (uint32)bcm_strtoul(val, NULL, 0);
3069 /* Ensure there is no bit set in min_mask which is not set in max_mask */
3070 max_mask |= min_mask;
3073 * min_mask register and then reset the bits which change from 1 to 0
3081 * min_mask register and then reset the bits which change from 1 to 0
3086 if (min_mask)
3087 OR_REG(osh, PMUREG(sih, max_res_mask), min_mask);
3091 if (min_mask) {
3092 PMU_MSG(("Changing min_res_mask to 0x%x\n", min_mask));
3093 W_REG(osh, PMUREG(sih, min_res_mask), min_mask);
4731 si_pmu_pll_off(si_t *sih, osl_t *osh, chipcregs_t *cc, uint32 *min_mask,
4737 *min_mask = R_REG(osh, PMUREG(sih, min_res_mask));
4776 si_pmu_pll_off_PARR(si_t *sih, osl_t *osh, uint32 *min_mask,
4788 *min_mask = R_REG(osh, PMUREG(sih, min_res_mask));
4940 uint32 min_mask = 0, max_mask = 0, clk_ctl_st = 0;
4967 si_pmu_pll_off(sih, osh, cc, &min_mask, &max_mask, &clk_ctl_st);
4979 si_pmu_pll_on(sih, osh, cc, min_mask, max_mask, clk_ctl_st);
5154 uint32 min_mask = 0, max_mask = 0, clk_ctl_st = 0;
5182 si_pmu_pll_off(sih, osh, cc, &min_mask, &max_mask, &clk_ctl_st);
5197 si_pmu_pll_on(sih, osh, cc, min_mask, max_mask, clk_ctl_st);
6784 uint32 min_mask = 0;
6804 si_pmu_res_masks(sih, &min_mask, &max_mask);
6807 min_mask = R_REG(osh, &cc->min_res_mask);
6809 deps &= ~min_mask;
6933 uint32 min_mask = 0;
6937 min_mask = R_REG(osh, PMUREG(sih, min_res_mask));
6938 *min_res_mask = min_mask;
6940 min_mask |= rsrcs;
6941 min_mask |= si_pmu_res_deps(sih, osh, cc, min_mask, TRUE);
6944 PMU_MSG(("Adding rsrc 0x%x to min_res_mask\n", min_mask));
6945 W_REG(osh, PMUREG(sih, min_res_mask), min_mask);
6958 min_mask = *min_res_mask;
6960 min_mask = R_REG(osh, PMUREG(sih, min_res_mask));
6962 min_mask &= ~rsrcs;
6967 min_mask |= si_pmu_res_deps(sih, osh, cc, min_mask, TRUE);
6968 on_check = ((min_mask & rsrcs) != 0);
6970 PMU_MSG(("Removing rsrc 0x%x from min_res_mask\n", min_mask));
6971 W_REG(osh, PMUREG(sih, min_res_mask), min_mask);
8706 uint32 min_mask = 0, max_mask = 0;
8730 si_pmu_res_masks(sih, &min_mask, &max_mask);
8731 max_mask = 0; /* Only care about min_mask for now */
8735 min_mask = PMURES_BIT(RES4335_LPLDO_PO);
8737 min_mask = PMURES_BIT(RES4335_WL_CORE_RDY) | PMURES_BIT(RES4335_OTP_PU);
8744 if (min_mask) {
8746 min_mask |= si_pmu_res_deps(sih, osh, cc, min_mask, FALSE);
8747 W_REG(osh, PMUREG(sih, min_res_mask), min_mask);