Lines Matching defs:max_res_mask
321 uint32 max_res_mask, min_res_mask, clk_ctl_st;
332 si_pmu_pll_off(sih, osh, cc, &min_res_mask, &max_res_mask, &clk_ctl_st);
335 si_pmu_pll_on(sih, osh, cc, min_res_mask, max_res_mask, clk_ctl_st);
3008 max_mask |= R_REG(osh, PMUREG(sih, max_res_mask));
3015 PMU_MSG(("Applying brmax=%s to max_res_mask\n", val));
3078 OR_REG(osh, PMUREG(sih, max_res_mask), max_mask);
3087 OR_REG(osh, PMUREG(sih, max_res_mask), min_mask);
3098 PMU_MSG(("Changing max_res_mask to 0x%x\n", max_mask));
3099 W_REG(osh, PMUREG(sih, max_res_mask), max_mask);
3175 oldmax = R_REG(osh, PMUREG(sih, max_res_mask));
3177 W_REG(osh, PMUREG(sih, max_res_mask), oldmax & ~PMURES_BIT(RES4328_BB_PLL_PU));
3198 W_REG(osh, PMUREG(sih, max_res_mask), oldmax);
3247 AND_REG(osh, PMUREG(sih, max_res_mask), ~PMURES_BIT(RES4328_BB_PLL_PU));
3251 AND_REG(osh, PMUREG(sih, max_res_mask), ~PMURES_BIT(RES5354_BB_PLL_PU));
4071 /* write to max_res_mask 0xBFFF: clear max_rsrc_mask */
4072 AND_REG(osh, PMUREG(sih, max_res_mask),
4075 /* write to max_res_mask 0xFFFF :set max_rsrc_mask */
4076 OR_REG(osh, PMUREG(sih, max_res_mask),
4200 uint32 min_res_mask = 0, max_res_mask = 0, clk_ctl_st = 0;
4206 si_pmu_pll_off(sih, osh, cc, &min_res_mask, &max_res_mask, &clk_ctl_st);
4279 si_pmu_pll_on(sih, osh, cc, min_res_mask, max_res_mask, clk_ctl_st);
4738 *max_mask = R_REG(osh, PMUREG(sih, max_res_mask));
4757 OR_REG(osh, PMUREG(sih, max_res_mask), ht_req);
4765 AND_REG(osh, PMUREG(sih, max_res_mask), ~ht_req);
4789 *max_mask = R_REG(osh, PMUREG(sih, max_res_mask));
4807 OR_REG(osh, PMUREG(sih, max_res_mask), ht_req);
4815 AND_REG(osh, PMUREG(sih, max_res_mask), ~ht_req);
4852 OR_REG(osh, PMUREG(sih, max_res_mask), max_mask_mask);
5033 AND_REG(osh, PMUREG(sih, max_res_mask),
5257 AND_REG(osh, PMUREG(sih, max_res_mask),
5267 AND_REG(osh, PMUREG(sih, max_res_mask),
5294 AND_REG(osh, PMUREG(sih, max_res_mask), ~(PMURES_BIT(RES4315_HT_AVAIL)));
5298 AND_REG(osh, PMUREG(sih, max_res_mask), ~(PMURES_BIT(RES4315_BBPLL_PWRSW_PU)));
5315 AND_REG(osh, PMUREG(sih, max_res_mask), ~(PMURES_BIT(RES4319_HT_AVAIL)));
5319 AND_REG(osh, PMUREG(sih, max_res_mask), ~(PMURES_BIT(RES4319_BBPLL_PWRSW_PU)));
5333 AND_REG(osh, PMUREG(sih, max_res_mask),
5343 AND_REG(osh, PMUREG(sih, max_res_mask),
5672 mask = R_REG(osh, PMUREG(sih, max_res_mask)) | PMURES_BIT(RES43602_PARLDO_PU);
5673 W_REG(osh, PMUREG(sih, max_res_mask), mask);
5882 maxmask = R_REG(osh, PMUREG(sih, max_res_mask));
5884 /* Make sure the PLL is off: clear bit 4 & 5 of min/max_res_mask */
5887 AND_REG(osh, PMUREG(sih, max_res_mask), ~(PMURES_BIT(RES4322_HT_SI_AVAIL)));
5890 AND_REG(osh, PMUREG(sih, max_res_mask), ~(PMURES_BIT(RES4322_SI_PLL_ON)));
5900 W_REG(osh, PMUREG(sih, max_res_mask), maxmask);
7136 uint32 min_res_mask = 0, max_res_mask = 0, clk_ctl_st = 0;
7173 si_pmu_pll_off(sih, osh, cc, &min_res_mask, &max_res_mask, &clk_ctl_st);
7180 si_pmu_pll_on(sih, osh, cc, min_res_mask, max_res_mask, clk_ctl_st);
7190 uint32 max_res_mask, uint32 clk_ctl_st, uint8 spuravoid)
7234 si_pmu_pll_on(sih, osh, cc, min_res_mask, max_res_mask, clk_ctl_st);
7803 maxmask = R_REG(osh, PMUREG(sih, max_res_mask));
7805 /* Make sure the PLL is off: clear bit 4 & 5 of min/max_res_mask */
7808 AND_REG(osh, PMUREG(sih, max_res_mask), ~(PMURES_BIT(RES4322_HT_SI_AVAIL)));
7811 AND_REG(osh, PMUREG(sih, max_res_mask), ~(PMURES_BIT(RES4322_SI_PLL_ON)));
7838 /* Restore min_res_mask and max_res_mask */
7840 W_REG(osh, PMUREG(sih, max_res_mask), maxmask);
8753 W_REG(osh, PMUREG(sih, max_res_mask), max_mask);