Lines Matching defs:freq_tgt
3763 uint32 freq_tgt; /* freq_target: N_divide_ratio bitfield in DFLL */
3767 * If a DFLL clock of 480Mhz is desired, use this table to determine xf and freq_tgt for
4991 uint32 freq_tgt, pll0;
5013 freq_tgt = (pll0 & PMU15_PLL_PC0_FREQTGT_MASK) >> PMU15_PLL_PC0_FREQTGT_SHIFT;
5014 if (freq_tgt == xt->freq_tgt) {
5043 pll0 = (pll0 & ~PMU15_PLL_PC0_FREQTGT_MASK) | (xt->freq_tgt << PMU15_PLL_PC0_FREQTGT_SHIFT);
5051 hsic_freq = pmu2_xtaltab0_adfll_480[xt_idx].freq_tgt;
5074 uint32 freq_tgt = 0, pll0 = 0;
5084 freq_tgt = (pll0 & PMU15_PLL_PC0_FREQTGT_MASK) >> PMU15_PLL_PC0_FREQTGT_SHIFT;
5092 if (xt->freq_tgt == freq_tgt)
5098 if (xt->freq_tgt == freq_tgt)
5112 uint32 freq_tgt, pll0;
5117 freq_tgt = (pll0 & PMU15_PLL_PC0_FREQTGT_MASK) >> PMU15_PLL_PC0_FREQTGT_SHIFT;
5121 if (xt->freq_tgt == freq_tgt)
5128 if (xt->freq_tgt == freq_tgt)
7647 pll0 |= (xt->freq_tgt << PMU15_PLL_PC0_FREQTGT_SHIFT);