Lines Matching refs:sih
161 config_cmd(si_t *sih, uint coreunit, uint bus, uint dev, uint func, uint off)
172 osh = si_osh(sih);
174 coreidx = si_coreidx(sih);
175 pci = (sbpciregs_t *)si_setcore(sih, PCI_CORE_ID, coreunit);
182 pcie = (sbpcieregs_t *)si_setcore(sih, PCIE_CORE_ID, coreunit);
188 (pcie_readreg(sih, pcie, PCIE_PCIEREGS,
192 si_setcoreidx(sih, coreidx);
229 si_setcoreidx(sih, coreidx);
245 si_pcihb_read_config(si_t *sih, uint coreunit, uint bus, uint dev, uint func,
260 osh = si_osh(sih);
263 coreidx = si_coreidx(sih);
264 pci = (sbpciregs_t *)si_setcore(sih, PCI_CORE_ID, coreunit);
266 if (si_corerev(sih) >= PCI_HBSBCFG_REV) {
275 pcie = (sbpcieregs_t *)si_setcore(sih, PCIE_CORE_ID, coreunit);
281 *val = pcie_readreg(sih, pcie, PCIE_CONFIGREGS,
291 si_setcoreidx(sih, coreidx);
297 extpci_read_config(si_t *sih, uint bus, uint dev, uint func, uint off, void *buf, int len)
316 if (!si_pcihb_read_config(sih, coreunit, bus, dev, func, off, ®, &val))
318 } else if (((addr = config_cmd(sih, coreunit, bus, dev, func, off)) == 0) ||
345 extpci_write_config(si_t *sih, uint bus, uint dev, uint func, uint off, void *buf, int len)
356 osh = si_osh(sih);
368 if (!si_pcihb_read_config(sih, coreunit, bus, dev, func, off, ®, &val))
370 } else if (((addr = config_cmd(sih, coreunit, bus, dev, func, off)) == 0) ||
396 coreidx = si_coreidx(sih);
399 pcie = (sbpcieregs_t *)si_setcore(sih, PCIE_CORE_ID, coreunit);
404 pcie_writereg(sih, pcie, PCIE_CONFIGREGS,
407 si_setcoreidx(sih, coreidx);
411 if ((CHIPID(sih->chip) == BCM4716_CHIP_ID) ||
412 (CHIPID(sih->chip) == BCM4748_CHIP_ID))
446 si_pcid_read_config(si_t *sih, uint coreidx, si_pci_cfg_t *cfg, uint off, uint len)
459 osh = si_osh(sih);
462 oldidx = si_coreidx(sih);
463 si_setcoreidx(sih, coreidx);
464 if (si_iscoreup(sih)) {
475 si_setcoreidx(sih, oldidx);
479 si_pcid_write_config(si_t *sih, uint coreidx, si_pci_cfg_t *cfg, uint off, uint len)
488 osh = si_osh(sih);
495 oldidx = si_coreidx(sih);
496 si_setcoreidx(sih, coreidx);
497 if (si_iscoreup(sih)) {
508 si_setcoreidx(sih, oldidx);
515 si_read_config(si_t *sih, uint bus, uint dev, uint func, uint off, void *buf, int len)
532 si_pcid_read_config(sih, dev, &si_pci_cfg[dev][func], off, len);
547 si_write_config(si_t *sih, uint bus, uint dev, uint func, uint off, void *buf, int len)
564 osh = si_osh(sih);
580 coreidx = si_coreidx(sih);
581 if ((regs = si_setcoreidx(sih, dev))) {
593 si_setcoreidx(sih, coreidx);
605 si_pcid_write_config(sih, dev, &si_pci_cfg[dev][func], off, len);
611 hndpci_read_config(si_t *sih, uint bus, uint dev, uint func, uint off, void *buf, int len)
614 return si_read_config(sih, bus, dev, func, off, buf, len);
616 return extpci_read_config(sih, bus, dev, func, off, buf, len);
620 hndpci_write_config(si_t *sih, uint bus, uint dev, uint func, uint off, void *buf, int len)
623 return si_write_config(sih, bus, dev, func, off, buf, len);
625 return extpci_write_config(sih, bus, dev, func, off, buf, len);
637 hndpci_find_pci_capability(si_t *sih, uint bus, uint dev, uint func,
646 hndpci_read_config(sih, bus, dev, func, PCI_CFG_HDR, &byte_val, sizeof(uint8));
651 hndpci_read_config(sih, bus, dev, func, PCI_CFG_STAT, &byte_val, sizeof(uint8));
656 hndpci_read_config(sih, bus, dev, func, PCI_CFG_CAPPTR, &cap_ptr, sizeof(uint8));
661 hndpci_read_config(sih, bus, dev, func, cap_ptr, &cap_id, sizeof(uint8));
663 hndpci_read_config(sih, bus, dev, func, cap_ptr + 1, &cap_ptr, sizeof(uint8));
666 hndpci_read_config(sih, bus, dev, func, cap_ptr, &cap_id, sizeof(uint8));
685 hndpci_read_config(sih, bus, dev, func, cap_data, buf, sizeof(uint8));
702 BCMATTACHFN(hndpci_init_pci)(si_t *sih, uint coreunit)
714 chip = sih->chip;
715 chiprev = sih->chiprev;
716 chippkg = sih->chippkg;
718 osh = si_osh(sih);
720 pci = (sbpciregs_t *)si_setcore(sih, PCI_CORE_ID, coreunit);
722 pcie = (sbpcieregs_t *)si_setcore(sih, PCIE_CORE_ID, coreunit);
732 if (sih->chipst & CST4706_PCIE1_DISABLE) {
754 si_core_reset(sih, 0, 0);
767 si_setint(sih, -1);
773 si_core_disable(sih, 0);
796 sb_commit(sih);
823 si_gpioout(sih, 1, 1, GPIO_DRV_PRIORITY);
824 si_gpioouten(sih, 1, 1, GPIO_DRV_PRIORITY);
889 cap_ptr = hndpci_find_pci_capability(sih, bus, pci_hbslot, 0,
894 hndpci_read_config(sih, bus, pci_hbslot, 0, root_cap,
900 hndpci_write_config(sih, bus, pci_hbslot, 0, root_ctrl,
917 SPINWAIT((hndpci_read_config(sih, bus, dev, 0,
928 hndpci_read_config(sih, bus, pci_hbslot, 0, PCI_CFG_DEVCTRL,
932 hndpci_write_config(sih, bus, pci_hbslot, 0, PCI_CFG_DEVCTRL,
938 hndpci_write_config(sih, bus, pci_hbslot, 0, PCI_CFG_CMD, &val, sizeof(val));
953 hndpci_arb_park(si_t *sih, uint parkid)
959 pci = (sbpciregs_t *)si_setcore(sih, PCI_CORE_ID, 0);
966 pcirev = si_corerev(sih);
987 arb = R_REG(si_osh(sih), &pci->arbcontrol);
990 W_REG(si_osh(sih), &pci->arbcontrol, arb);
995 hndpci_deinit_pci(si_t *sih, uint coreunit)
1004 coreidx = si_coreidx(sih);
1005 pci = (sbpciregs_t *)si_setcore(sih, PCI_CORE_ID, coreunit);
1007 pcie = (sbpcieregs_t *)si_setcore(sih, PCIE_CORE_ID, coreunit);
1015 W_REG(si_osh(sih), &pci->control, PCI_RST_OE);
1017 W_REG(si_osh(sih), &pcie->control, PCIE_RST_OE);
1019 si_core_disable(sih, 0);
1020 si_setcoreidx(sih, coreidx);
1028 hndpci_deinit(si_t *sih)
1033 hndpci_deinit_pci(sih, coreunit);
1040 BCMATTACHFN(hndpci_init_regions)(si_t *sih, uint func, pci_config_regs *cfg, si_bar_cfg_t *bar)
1042 bool issb = sih->socitype == SOCI_SB;
1047 if ((si_coreid(sih) == USB20H_CORE_ID) ||
1048 (si_coreid(sih) == NS_USB20_CORE_ID)) {
1050 if (si_coreid(sih) == USB20H_CORE_ID) {
1054 base = htol32(si_addrspace(sih, 0));
1060 if (((CHIPID(sih->chip) == BCM5357_CHIP_ID) ||
1061 (CHIPID(sih->chip) == BCM4749_CHIP_ID)) &&
1062 CHIPREV(sih->chiprev) == 0)
1065 base = htol32(si_addrspace(sih, 1));
1072 bar->n = n = si_numaddrspaces(sih);
1074 int size = si_addrspacesize(sih, i);
1077 cfg->base[i] = htol32(si_addrspace(sih, i));
1092 BCMATTACHFN(hndpci_init_cores)(si_t *sih)
1106 chiprev = sih->chiprev;
1107 coreidx = si_coreidx(sih);
1109 osh = si_osh(sih);
1120 if (!(regs = si_setcoreidx(sih, dev)))
1124 coreid = si_coreid(sih);
1132 if (((CHIPID(sih->chip) == BCM5357_CHIP_ID) ||
1133 (CHIPID(sih->chip) == BCM4749_CHIP_ID)) &&
1134 (sih->chippkg == BCM5357_PKG_ID)) {
1140 if ((CHIPID(sih->chip) == BCM4706_CHIP_ID)) {
1143 if (si_coreunit(sih) > 0) {
1157 if (si_corepciid(sih, func, &vendor, &device, &class, &subclass,
1188 hndpci_init_regions(sih, func, cfg, bar);
1190 cfg->int_pin = si_flag(sih);
1192 cfg->int_line = si_irq(sih);
1206 si_setcoreidx(sih, coreidx);
1215 BCMATTACHFN(hndpci_init)(si_t *sih)
1220 status |= hndpci_init_pci(sih, coreunit);
1221 hndpci_init_cores(sih);