Lines Matching refs:sih
75 BCMINITFN(si_irq)(si_t *sih)
85 BCMATTACHFN(si_arm_init)(si_t *sih)
91 BCMINITFN(si_cpu_clock)(si_t *sih)
95 osh = si_osh(sih);
97 if (BCM4707_CHIP(CHIPID(sih->chip))) {
110 return si_clock(sih);
114 BCMINITFN(si_mem_clock)(si_t *sih)
121 osh = si_osh(sih);
123 if (BCM4707_CHIP(CHIPID(sih->chip))) {
124 chipcb = si_setcore(sih, NS_CCB_CORE_ID, 0);
139 return si_clock(sih);
143 BCMINITFN(si_arm_setclock)(si_t *sih, uint32 armclock, uint32 ddrclock, uint32 axiclock)
151 osh = si_osh(sih);
153 if (BCM4707_CHIP(CHIPID(sih->chip))) {
155 void *regs = (void *)si_setcore(sih, NS_DDR23_CORE_ID, 0);
157 ddr_flag = ((si_core_sflags(sih, 0, 0) & DDR_TYPE_MASK)
161 switch (sih->chippkg) {
163 if (CHIPID(sih->chip) == BCM47094_CHIP_ID) {
170 if (CHIPID(sih->chip) == BCM47094_CHIP_ID) {
194 if (ddrclock && si_mem_clock(sih) != ddrclock) {
203 bootdev = soc_boot_dev((void *)sih);
261 void si_mem_setclock(si_t *sih, uint32 ddrclock)
275 osh = si_osh(sih);
276 chipcb = (chipcommonbregs_t *)si_setcore(sih, NS_CCB_CORE_ID, 0);
302 hnd_cpu_reset(si_t *sih)
304 si_watchdog(sih, 1);