Lines Matching refs:sii
37 (sii->coreid[sii->curidx] == MIPS74K_CORE_ID))
42 (sii->coreid[sii->curidx] == USB20H_CORE_ID))
44 (sii->coreid[sii->curidx] == NS_CCB_CORE_ID))
118 ai_hwfixup(si_info_t *sii)
128 if (BUSTYPE(sii->pub.bustype) == SI_BUS &&
129 ((CHIPID(sii->pub.chip) == BCM4716_CHIP_ID) ||
130 (CHIPID(sii->pub.chip) == BCM4748_CHIP_ID))) {
133 ASSERT(sii->coreid[3] == MIPS74K_CORE_ID);
134 cpu = REG_MAP(sii->wrapba[3], SI_CORE_SIZE);
135 ASSERT(sii->coreid[5] == PCIE_CORE_ID);
136 pcie = REG_MAP(sii->wrapba[5], SI_CORE_SIZE);
137 ASSERT(sii->coreid[8] == I2S_CORE_ID);
138 i2s = REG_MAP(sii->wrapba[8], SI_CORE_SIZE);
139 if ((R_REG(sii->osh, &cpu->oobselina74) != 0x08060504) ||
140 (R_REG(sii->osh, &pcie->oobselina74) != 0x08060504) ||
141 (R_REG(sii->osh, &i2s->oobselouta30) != 0x88)) {
145 W_REG(sii->osh, &cpu->oobselina74, 0x07060504);
146 W_REG(sii->osh, &pcie->oobselina74, 0x07060504);
147 W_REG(sii->osh, &i2s->oobselouta30, 0x87);
205 si_info_t *sii = SI_INFO(sih);
206 uint i, coreid = sii->coreid[sii->curidx];
229 si_info_t *sii = SI_INFO(sih);
233 erombase = R_REG(sii->osh, &cc->eromptr);
242 sii->curwrap = (void *)((uintptr)regs + SI_CORE_SIZE);
245 OSL_PCI_WRITE_CONFIG(sii->osh, PCI_BAR0_WIN, 4, erombase);
276 SI_VMSG(("Found END of erom after %d cores\n", sii->numcores));
277 ai_hwfixup(sii);
312 sii->oob_router = addrl;
319 idx = sii->numcores;
321 sii->cia[idx] = cia;
322 sii->cib[idx] = cib;
323 sii->coreid[idx] = remap_coreid(sih, cid);
363 sii->coresba[idx] = addrl;
364 sii->coresba_size[idx] = sizel;
371 sii->coresba2[idx] = addrl;
372 sii->coresba2_size[idx] = sizel;
407 sii->wrapba[idx] = addrl;
418 ASSERT(sii->num_br < SI_MAXBR);
419 sii->br_wrapba[sii->num_br++] = addrl;
430 sii->wrapba[idx] = addrl;
435 i = (R_REG(sii->osh, &cc->chipid) & CID_PKG_MASK) >> CID_PKG_SHIFT;
439 for (j = 0; j < sii->numcores; j++) {
440 if (sii->coreid[j] == GMAC_CORE_ID)
443 if (j != sii->numcores) {
456 sii->numcores++;
462 sii->numcores = 0;
472 si_info_t *sii = SI_INFO(sih);
476 if (coreidx >= MIN(sii->numcores, SI_MAXCORES))
479 addr = sii->coresba[coreidx];
480 wrap = sii->wrapba[coreidx];
486 ASSERT((sii->intrsenabled_fn == NULL) || !(*(sii)->intrsenabled_fn)((sii)->intr_arg));
491 if (!sii->regs[coreidx]) {
492 sii->regs[coreidx] = REG_MAP(addr, SI_CORE_SIZE);
493 ASSERT(GOODREGS(sii->regs[coreidx]));
495 sii->curmap = regs = sii->regs[coreidx];
496 if (!sii->wrappers[coreidx] && (wrap != 0)) {
497 sii->wrappers[coreidx] = REG_MAP(wrap, SI_CORE_SIZE);
498 ASSERT(GOODREGS(sii->wrappers[coreidx]));
500 sii->curwrap = sii->wrappers[coreidx];
505 OSL_PCI_WRITE_CONFIG(sii->osh, PCI_BAR0_WIN, 4, addr);
506 regs = sii->curmap;
508 if (PCIE_GEN2(sii))
509 OSL_PCI_WRITE_CONFIG(sii->osh, PCIE2_BAR0_WIN2, 4, wrap);
511 OSL_PCI_WRITE_CONFIG(sii->osh, PCI_BAR0_WIN2, 4, wrap);
516 sii->curmap = regs = (void *)((uintptr)addr);
517 sii->curwrap = (void *)((uintptr)wrap);
528 sii->curmap = regs;
529 sii->curidx = coreidx;
537 si_info_t *sii = SI_INFO(sih);
544 for (i = 0; i < sii->numcores; i++) {
545 if (sii->coreid[i] == CC_CORE_ID) {
546 cc = (chipcregs_t *)sii->regs[i];
553 erombase = R_REG(sii->osh, &cc->eromptr);
557 cidx = sii->curidx;
558 cia = sii->cia[cidx];
559 cib = sii->cib[cidx];
630 si_info_t *sii;
633 sii = SI_INFO(sih);
634 cidx = sii->curidx;
637 return sii->coresba[cidx];
639 return sii->coresba2[cidx];
651 si_info_t *sii;
654 sii = SI_INFO(sih);
655 cidx = sii->curidx;
658 return sii->coresba_size[cidx];
660 return sii->coresba2_size[cidx];
671 si_info_t *sii;
674 sii = SI_INFO(sih);
677 return sii->curidx;
681 return sii->curidx;
686 return sii->curidx;
688 ai = sii->curwrap;
690 return (R_REG(sii->osh, &ai->oobselouta30) & 0x1f);
696 si_info_t *sii;
699 sii = SI_INFO(sih);
702 return sii->curidx;
706 return sii->curidx;
711 return sii->curidx;
713 ai = sii->curwrap;
715 return ((R_REG(sii->osh, &ai->oobselouta30) >> AI_OOBSEL_1_SHIFT) & AI_OOBSEL_MASK);
726 si_info_t *sii = SI_INFO(sih);
727 uint32 *map = (uint32 *) sii->curwrap;
730 uint32 w = R_REG(sii->osh, map+(offset/4));
733 W_REG(sii->osh, map+(offset/4), w);
736 return (R_REG(sii->osh, map+(offset/4)));
742 si_info_t *sii;
745 sii = SI_INFO(sih);
746 cia = sii->cia[sii->curidx];
753 si_info_t *sii;
756 sii = SI_INFO(sih);
758 cib = sii->cib[sii->curidx];
765 si_info_t *sii;
768 sii = SI_INFO(sih);
769 ai = sii->curwrap;
771 return (((R_REG(sii->osh, &ai->ioctrl) & (SICF_FGC | SICF_CLOCK_EN)) == SICF_CLOCK_EN) &&
772 ((R_REG(sii->osh, &ai->resetctrl) & AIRC_RESET) == 0));
792 si_info_t *sii;
794 sii = SI_INFO(sih);
807 if (!sii->regs[coreidx]) {
808 sii->regs[coreidx] = REG_MAP(sii->coresba[coreidx],
810 ASSERT(GOODREGS(sii->regs[coreidx]));
812 r = (uint32 *)((uchar *)sii->regs[coreidx] + regoff);
816 if ((sii->coreid[coreidx] == CC_CORE_ID) && SI_FAST(sii)) {
820 r = (uint32 *)((char *)sii->curmap + PCI_16KB0_CCREGS_OFFSET + regoff);
821 } else if (sii->pub.buscoreidx == coreidx) {
826 if (SI_FAST(sii))
827 r = (uint32 *)((char *)sii->curmap +
830 r = (uint32 *)((char *)sii->curmap +
838 INTR_OFF(sii, intr_val);
841 origidx = si_coreidx(&sii->pub);
844 r = (uint32*) ((uchar*) ai_setcoreidx(&sii->pub, coreidx) + regoff);
850 w = (R_REG(sii->osh, r) & ~mask) | val;
851 W_REG(sii->osh, r, w);
855 w = R_REG(sii->osh, r);
860 ai_setcoreidx(&sii->pub, origidx);
862 INTR_RESTORE(sii, intr_val);
882 si_info_t *sii;
884 sii = SI_INFO(sih);
896 if (!sii->regs[coreidx]) {
897 sii->regs[coreidx] = REG_MAP(sii->coresba[coreidx],
899 ASSERT(GOODREGS(sii->regs[coreidx]));
901 r = (uint32 *)((uchar *)sii->regs[coreidx] + regoff);
905 if ((sii->coreid[coreidx] == CC_CORE_ID) && SI_FAST(sii)) {
909 r = (uint32 *)((char *)sii->curmap + PCI_16KB0_CCREGS_OFFSET + regoff);
910 } else if (sii->pub.buscoreidx == coreidx) {
915 if (SI_FAST(sii))
916 r = (uint32 *)((char *)sii->curmap +
919 r = (uint32 *)((char *)sii->curmap +
935 si_info_t *sii;
940 sii = SI_INFO(sih);
942 ASSERT(GOODREGS(sii->curwrap));
943 ai = sii->curwrap;
946 if (R_REG(sii->osh, &ai->resetctrl) & AIRC_RESET)
950 SPINWAIT(((status = R_REG(sii->osh, &ai->resetstatus)) != 0), 300);
956 SPINWAIT(((status = R_REG(sii->osh, &ai->resetstatus)) != 0), 10000);
966 W_REG(sii->osh, &ai->resetctrl, AIRC_RESET);
967 dummy = R_REG(sii->osh, &ai->resetctrl);
971 W_REG(sii->osh, &ai->ioctrl, bits);
972 dummy = R_REG(sii->osh, &ai->ioctrl);
985 si_info_t *sii;
990 sii = SI_INFO(sih);
991 ASSERT(GOODREGS(sii->curwrap));
992 ai = sii->curwrap;
995 SPINWAIT(((dummy = R_REG(sii->osh, &ai->resetstatus)) != 0), 300);
999 W_REG(sii->osh, &ai->resetctrl, AIRC_RESET);
1003 SPINWAIT((R_REG(sii->osh, &ai->resetstatus) != 0), 300);
1005 W_REG(sii->osh, &ai->ioctrl, (bits | resetbits | SICF_FGC | SICF_CLOCK_EN));
1006 dummy = R_REG(sii->osh, &ai->ioctrl);
1010 SPINWAIT(((dummy = R_REG(sii->osh, &ai->resetstatus)) != 0), 300);
1013 while (R_REG(sii->osh, &ai->resetctrl) != 0 && --loop_counter != 0) {
1015 SPINWAIT(((dummy = R_REG(sii->osh, &ai->resetstatus)) != 0), 300);
1019 W_REG(sii->osh, &ai->resetctrl, 0);
1022 SPINWAIT((R_REG(sii->osh, &ai->resetstatus) != 0), 300);
1026 W_REG(sii->osh, &ai->ioctrl, (bits | SICF_CLOCK_EN));
1027 dummy = R_REG(sii->osh, &ai->ioctrl);
1035 si_info_t *sii;
1039 sii = SI_INFO(sih);
1057 ASSERT(GOODREGS(sii->curwrap));
1058 ai = sii->curwrap;
1063 w = ((R_REG(sii->osh, &ai->ioctrl) & ~mask) | val);
1064 W_REG(sii->osh, &ai->ioctrl, w);
1071 si_info_t *sii;
1075 sii = SI_INFO(sih);
1092 ASSERT(GOODREGS(sii->curwrap));
1093 ai = sii->curwrap;
1098 w = ((R_REG(sii->osh, &ai->ioctrl) & ~mask) | val);
1099 W_REG(sii->osh, &ai->ioctrl, w);
1102 return R_REG(sii->osh, &ai->ioctrl);
1108 si_info_t *sii;
1112 sii = SI_INFO(sih);
1129 ASSERT(GOODREGS(sii->curwrap));
1130 ai = sii->curwrap;
1136 w = ((R_REG(sii->osh, &ai->iostatus) & ~mask) | val);
1137 W_REG(sii->osh, &ai->iostatus, w);
1140 return R_REG(sii->osh, &ai->iostatus);
1148 si_info_t *sii;
1153 sii = SI_INFO(sih);
1154 osh = sii->osh;
1156 for (i = 0; i < sii->numcores; i++) {
1157 si_setcoreidx(&sii->pub, i);
1158 ai = sii->curwrap;
1160 bcm_bprintf(b, "core 0x%x: \n", sii->coreid[i]);
1202 if ((sih->chip == BCM4331_CHIP_ID) && (sii->coreid[i] == PCIE_CORE_ID)) {
1204 OSL_PCI_WRITE_CONFIG(sii->osh, PCI_BAR0_WIN2, 4, 0x18103000);
1316 si_info_t *sii;
1321 sii = SI_INFO(sih);
1322 ai = sii->curwrap;
1323 osh = sii->osh;
1336 cid = sii->coreid[sii->curidx];
1337 addr = sii->wrapba[sii->curidx];
1344 si_info_t *sii;
1350 sii = SI_INFO(sih);
1351 osh = sii->osh;
1352 for (i = 0; i < sii->numcores; i++) {
1366 ai = sii->curwrap;
1367 cid = sii->coreid[sii->curidx];
1368 addr = sii->wrapba[sii->curidx];
1370 if ((sih->chip == BCM4331_CHIP_ID) && (sii->coreid[i] == PCIE_CORE_ID)) {
1372 OSL_PCI_WRITE_CONFIG(sii->osh, PCI_BAR0_WIN2, 4, 0x18103000);
1374 OSL_PCI_WRITE_CONFIG(sii->osh, PCI_BAR0_WIN2, 4, 0x18104000);
1376 OSL_PCI_WRITE_CONFIG(sii->osh, PCI_BAR0_WIN2, 4, 0x18105000);
1387 si_info_t *sii = SI_INFO(sih);
1391 for (i = 0; i < sii->num_br; ++i) {
1392 ai = (aidmp_t *) sii->br_wrapba[i];
1393 W_REG(sii->osh, &ai->errlogctrl, (1 << AIELC_TO_ENAB_SHIFT) |
1403 si_info_t *sii = SI_INFO(sih);
1407 for (i = 0; i < sii->num_br; ++i) {
1408 ai = (aidmp_t *) sii->br_wrapba[i];
1410 if (R_REG(sii->osh, &ai->errlogstatus) & AIELS_TIMEOUT_MASK) {
1412 W_REG(sii->osh, &ai->errlogdone, AIELD_ERRDONE_MASK);
1415 while (R_REG(sii->osh, &ai->errlogstatus) & AIELS_TIMEOUT_MASK)
1419 OR_REG(sii->osh, &ai->resetctrl, AIRC_RESET);
1421 (void)R_REG(sii->osh, &ai->resetctrl);
1423 AND_REG(sii->osh, &ai->resetctrl, ~(AIRC_RESET));
1425 (void)R_REG(sii->osh, &ai->resetctrl);