Lines Matching refs:ddr_write
1114 #define ddr_write(offset, value) \
1136 ddr_write(DDR23PHY_ZQ_PVT_COMP_CTL, 0x04000000);
1163 ddr_write(DDR23PHY_PLL_CONFIG, 0x8000000c);
1164 ddr_write(DDR23PHY_PLL_PRE_DIVIDER,
1166 ddr_write(DDR23PHY_PLL_DIVIDER, 0x02000000);
1167 ddr_write(DDR23PHY_PLL_CONFIG, 0x80000008);
1178 ddr_write(DDR23PHY_PLL_CONFIG, 0x80000000);
1179 ddr_write(DDR23PHY_PLL_CONFIG, 0x00000000);
1186 ddr_write(DDR23PHY_BL3_VDL_CALIBRATE, 0x00000003);
1187 ddr_write(DDR23PHY_BL2_VDL_CALIBRATE, 0x00000003);
1188 ddr_write(DDR23PHY_BL1_VDL_CALIBRATE, 0x00000003);
1189 ddr_write(DDR23PHY_BL0_VDL_CALIBRATE, 0x00000003);
1231 ddr_write(AI_RESETCTRL, 0x00000000)
1237 ddr_write(PL341_refresh_prd, MEMCYCLES_MIN(CFG_DDR_REFRESH_PRD));
1242 ddr_write(PL341_t_mrd, MEMCYCLES(CFG_DDR_T_MRD));
1247 ddr_write(PL341_t_ras, MEMCYCLES(CFG_DDR_T_RAS));
1252 ddr_write(PL341_t_rc, MEMCYCLES(CFG_DDR_T_RC));
1257 ddr_write(PL341_t_rcd, MEMCYCLES(CFG_DDR_T_RCD));
1262 ddr_write(PL341_t_rfc,
1268 ddr_write(PL341_t_rp,
1274 ddr_write(PL341_t_rrd, MEMCYCLES(CFG_DDR_T_RRD));
1279 ddr_write(PL341_t_wr, MEMCYCLES(CFG_DDR_T_WR));
1284 ddr_write(PL341_t_wtr, MEMCYCLES(CFG_DDR_T_WTR));
1289 ddr_write(PL341_t_xp, MEMCYCLES(CFG_DDR_T_XP));
1294 ddr_write(PL341_t_xsr, MEMCYCLES(CFG_DDR_T_XSR));
1299 ddr_write(PL341_t_esr, MEMCYCLES(CFG_DDR_T_ESR));
1304 ddr_write(PL341_t_faw,
1384 ddr_write(PL341_chip_0_cfg, 0x00000000);
1387 ddr_write(PL341_user_config0, 0x00000003);
1394 ddr_write(PL341_direct_cmd, MCHIP_CMD_NOP);
1397 ddr_write(PL341_direct_cmd, MCHIP_CMD_PRECHARGE_ALL);
1400 ddr_write(PL341_direct_cmd, MCHIP_CMD_MODE_REG | MCHIP_MODEREG_SEL(2));
1403 ddr_write(PL341_direct_cmd, MCHIP_CMD_MODE_REG | MCHIP_MODEREG_SEL(3));
1406 ddr_write(PL341_direct_cmd,
1422 ddr_write(PL341_direct_cmd, MCHIP_CMD_PRECHARGE_ALL);
1425 ddr_write(PL341_direct_cmd, MCHIP_CMD_AUTO_REFRESH);
1426 ddr_write(PL341_direct_cmd, MCHIP_CMD_AUTO_REFRESH);
1433 ddr_write(PL341_direct_cmd,
1440 ddr_write(PL341_direct_cmd,
1447 ddr_write(PL341_direct_cmd,
1454 ddr_write(PL341_memc_cmd, 0);