Lines Matching refs:and
6 * Permission to use, copy, modify, and/or distribute this software for any
8 * copyright notice and this permission notice appear in all copies.
40 * and previous chips. Also, it changes k0 and k1 registers.
246 and t1,t0,ER_TAG
258 and s4,t0,CIA_CID_MASK
282 * to do. This will change if/when we have an AI chip with MIPS and
303 and a1,a1,t2
315 and t1,t0,ER_TAG
321 addesc: and t1,t0,AD_ST_MASK
327 swrap: and a2,t0,t2
339 and t0,t0,s6
344 * check the corerev and use chipstatus for those two.
346 and t3,t3,CIB_REV_MASK
361 and a3,t0,t1 # a3 == 4 if ddr2, 2 if ddr1, 1 if sdr.
369 and t0,t0,t1
386 and t4,t4,s6
391 and t4,t4,t5
402 /* skip bad blocks and locate nvram */
443 /* Try embedded NVRAM at 4 KB and 1 KB as last resorts */
466 /* Use DDR1M16MX16 if QT and DDR1M32MX16 otherwise */
476 /* For ddr2, use DDR2M32X16X2 if QT and DDR2M128X16X2 otherwise */
573 and t1,t1,t2
582 and t0,t0,s6
608 and t0,t0,s0 # delay_dqs_0
612 and t1,t1,t2
617 and t0,t0,s8 # delay_dqs_1
620 and t1,t1,t2
625 and t0,t0,s0 # clk_wr_delay_0
629 and t1,t1,t2
634 and t0,t0,s8 # clk_wr_delay_1
637 and t1,t1,t2
646 and t0,t0,s0 # delay_dqs_0
650 and t0,t0,s0 # clk_wr_delay
666 and t0,t0,t1
671 and t2,t2,t1
676 and t0,t0,t1
681 and t2,t2,t1
689 and t0,t0,s0
704 and t0,t0,s0
723 and t0,t0,t1
730 and t0,t0,t1
734 /* Set the right value for column size and CAS latency */
738 and t0,t0,s0
747 and t1,0xf00
750 and t1,0x300
752 and t2,~0xf00
757 and t2,~0x70
765 and t2,~0xf00
770 and t2,~0xf0000
774 /* Set caslat_lin and caslat_lin_gate */
790 addi t0,t0,-1 # and -1 => caslin_gate
799 and t0,t0,s0
835 and t0,t0,t1
881 and t1,t0,DM_INT_INIT_DONE
887 and t0,t0,t1
894 and t2,t2,t0
901 and t2,t2,t0
905 and t0,t0,t1
914 and t2,t2,t0
921 and t2,t2,t0
925 and t0,t0,t1
932 and t0,t0,t1 # t0 = control133 & mask
935 and t2,t1,t2 # t2 = control132 & ~mask
936 or t0,t0,t2 # Or them and ...
942 and t1,t0,DM_INT_INIT_DONE
947 and t0,t0,t1 # t0 = control24 & mask
950 and t2,t1,t2 # t2 = control23 & ~mask
951 or t0,t0,t2 # Or them and ...
965 /* Read back and delay */
974 /* Read back and delay */
983 /* Read back and delay */
1032 and t8,t8,t9
1041 and t8,t8,t9
1063 and t7,t8,v0
1077 and t7,t8,t9
1082 and t7,t8,t9
1088 and t7,t8,t9
1110 * This routine deals with DDR23_PHY and PL341 MEMC.
1140 and t1, t1, t2;
1173 and t1, t1, t2;
1193 1: /* Wait until calib_idle == 1 and locked for all BL */
1195 and t1, t1, t2;
1199 and t1, t1, t2;
1203 and t1, t1, t2;
1207 and t1, t1, t2;
1309 and t1, s0, 0xffff
1336 /* PL341_memory_cfg: Rows and Columns */
1344 and t2, t2, t3 # clear column
1353 /* PL341_memory_cfg2: Bus width and Banks */
1360 and t2, t2, t3 # Clear bit[7:6] to work in 16-bit mode
1378 and t2, t2, t3 # Clear bit[5:4] to work in 4-bank mode
1429 and t2, t2, ~MCHIP_MR_DLL_RESET(1)