Lines Matching refs:ddr
791 ddr_regs_init(si_t *sih, ddrcregs_t *ddr, unsigned int ddr_table[])
800 W_REG(osh, &ddr->control[reg_num], reg_val);
807 ddrcregs_t *ddr;
813 ddr = (ddrcregs_t *)si_setcore((si_t *)sih, NS_DDR23_CORE_ID, 0);
814 if (!ddr) {
819 val = R_REG(osh, &ddr->control[89]);
821 W_REG(osh, &ddr->control[89], val);
825 W_REG(osh, &ddr->control[43], val);
829 W_REG(osh, &ddr->control[43], val);
832 if (R_REG(osh, &ddr->control[89]) & (1 << 18)) {
838 if (j == 0 && (R_REG(osh, &ddr->control[89]) & (1 << 18)) == 0) {
1112 ddrcregs_t *ddr;
1153 ddr = (ddrcregs_t *)si_setcore(sih, NS_DDR23_CORE_ID, 0);
1154 if (!ddr)
1158 val = R_REG(osh, &ddr->control[0]);
1222 val = R_REG(osh, &ddr->phy_control_rev);
1232 W_REG(osh, &ddr->phy_control_plldividers, 0x00000c10); /* high sku ? */
1268 W_REG(osh, &ddr->phy_control_pllconfig, val);
1272 val = R_REG(osh, &ddr->phy_control_pllstatus);
1281 W_REG(osh, &ddr->phy_ln0_rddata_dly, 3); /* high sku? */
1294 W_REG(osh, &ddr->phy_ln0_wr_premb_mode, val);
1297 W_REG(osh, &ddr->phy_control_zq_pvt_compctl, (1 << 20));
1300 W_REG(osh, &ddr->phy_control_vdl_calibrate, 0x08000101); /* high sku? */
1304 val = R_REG(osh, &ddr->phy_control_vdl_calibsts);
1320 ddr_regs_init(sih, ddr, ddr3_init_tab_1600);
1322 ddr_regs_init(sih, ddr, ddr2_init_tab_400);
1327 W_REG(osh, &ddr->phy_ln0_vdl_ovride_byte1_r_n, 0x00010120);
1328 W_REG(osh, &ddr->phy_ln0_vdl_ovride_byte0_bit_rd_en, 0x0001000d);
1329 W_REG(osh, &ddr->phy_ln0_vdl_ovride_byte1_bit_rd_en, 0x00010020);
1336 val = R_REG(osh, &ddr->control[21]);
1339 W_REG(osh, &ddr->control[21], val);
1341 val = R_REG(osh, &ddr->control[22]);
1344 W_REG(osh, &ddr->control[22], val);
1350 val = R_REG(osh, &ddr->control[87]);
1353 W_REG(osh, &ddr->control[87], val);
1355 val = R_REG(osh, &ddr->control[82]);
1367 W_REG(osh, &ddr->control[82], val);
1376 val = R_REG(osh, &ddr->control[5]);
1379 W_REG(osh, &ddr->control[5], val);
1381 val = R_REG(osh, &ddr->control[6]);
1384 W_REG(osh, &ddr->control[6], val);
1386 val = R_REG(osh, &ddr->control[174]);
1389 W_REG(osh, &ddr->control[174], val);
1391 val = R_REG(osh, &ddr->control[186]);
1394 W_REG(osh, &ddr->control[186], val);
1397 val = R_REG(osh, &ddr->control[44]);
1400 W_REG(osh, &ddr->control[44], val);
1402 val = R_REG(osh, &ddr->control[45]);
1410 W_REG(osh, &ddr->control[45], val);
1412 val = R_REG(osh, &ddr->control[206]);
1415 W_REG(osh, &ddr->control[206], val);
1417 val = R_REG(osh, &ddr->control[44]);
1420 W_REG(osh, &ddr->control[44], val);
1425 val = R_REG(osh, &ddr->control[0]);
1427 W_REG(osh, &ddr->control[0], val);
1428 while (!(R_REG(osh, &ddr->control[89]) & DDR_INT_INIT_DONE));
1430 W_REG(osh, &ddr->phy_ln0_rddata_dly, 3); /* high sku? */