Lines Matching refs:ssicr
136 unsigned long ssicr = SSIREG(SSICR);
143 pr_debug("ssi_hw_params() enter\nssicr was %08lx\n", ssicr);
146 ssicr &= ~(CR_TRMD | CR_CHNL_MASK | CR_DWL_MASK | CR_PDTA |
151 ssicr |= CR_TRMD; /* transmit */
158 ssicr |= ((channels >> 1) - 1) << CR_CHNL_SHIFT;
169 ssicr |= i << CR_DWL_SHIFT;
187 /*ssicr |= CR_PDTA;*/ /* cpu/data endianness ? */
198 ssicr |= i << CR_SWL_SHIFT;
205 SSIREG(SSICR) = ssicr;
207 pr_debug("ssi_hw_params() leave\nssicr is now %08lx\n", ssicr);
228 unsigned long ssicr;
232 ssicr = SSIREG(SSICR) & ~CR_CKDIV_MASK;
238 SSIREG(SSICR) = ssicr | (i << CR_CKDIV_SHIFT);
251 unsigned long ssicr = SSIREG(SSICR);
253 pr_debug("ssi_set_fmt()\nssicr was 0x%08lx\n", ssicr);
255 ssicr &= ~(CR_DEL | CR_PDTA | CR_BREN | CR_SWSP | CR_SCKP |
262 ssicr |= CR_DEL | CR_PDTA;
265 ssicr |= CR_DEL;
276 ssicr |= CR_BREN;
282 ssicr |= CR_SCKP; /* sample data at low clkedge */
285 ssicr |= CR_SCKP | CR_SWSP;
290 ssicr |= CR_SWSP; /* word select starts low */
301 ssicr |= CR_SCK_MASTER;
304 ssicr |= CR_SWS_MASTER;
307 ssicr |= CR_SWS_MASTER | CR_SCK_MASTER;
314 SSIREG(SSICR) = ssicr;
315 pr_debug("ssi_set_fmt() leave\nssicr is now 0x%08lx\n", ssicr);