Lines Matching refs:s3c_ac97
39 static struct s3c_ac97_info s3c_ac97;
72 stat = readl(s3c_ac97.regs + S3C_AC97_GLBSTAT) & 0x7;
76 INIT_COMPLETION(s3c_ac97.done);
78 ac_glbctrl = readl(s3c_ac97.regs + S3C_AC97_GLBCTRL);
80 writel(ac_glbctrl, s3c_ac97.regs + S3C_AC97_GLBCTRL);
84 writel(ac_glbctrl, s3c_ac97.regs + S3C_AC97_GLBCTRL);
87 ac_glbctrl = readl(s3c_ac97.regs + S3C_AC97_GLBCTRL);
89 writel(ac_glbctrl, s3c_ac97.regs + S3C_AC97_GLBCTRL);
91 if (!wait_for_completion_timeout(&s3c_ac97.done, HZ))
101 mutex_lock(&s3c_ac97.lock);
105 INIT_COMPLETION(s3c_ac97.done);
107 ac_codec_cmd = readl(s3c_ac97.regs + S3C_AC97_CODEC_CMD);
109 writel(ac_codec_cmd, s3c_ac97.regs + S3C_AC97_CODEC_CMD);
113 ac_glbctrl = readl(s3c_ac97.regs + S3C_AC97_GLBCTRL);
115 writel(ac_glbctrl, s3c_ac97.regs + S3C_AC97_GLBCTRL);
117 if (!wait_for_completion_timeout(&s3c_ac97.done, HZ))
120 stat = readl(s3c_ac97.regs + S3C_AC97_STAT);
127 mutex_unlock(&s3c_ac97.lock);
137 mutex_lock(&s3c_ac97.lock);
141 INIT_COMPLETION(s3c_ac97.done);
143 ac_codec_cmd = readl(s3c_ac97.regs + S3C_AC97_CODEC_CMD);
145 writel(ac_codec_cmd, s3c_ac97.regs + S3C_AC97_CODEC_CMD);
149 ac_glbctrl = readl(s3c_ac97.regs + S3C_AC97_GLBCTRL);
151 writel(ac_glbctrl, s3c_ac97.regs + S3C_AC97_GLBCTRL);
153 if (!wait_for_completion_timeout(&s3c_ac97.done, HZ))
156 ac_codec_cmd = readl(s3c_ac97.regs + S3C_AC97_CODEC_CMD);
158 writel(ac_codec_cmd, s3c_ac97.regs + S3C_AC97_CODEC_CMD);
160 mutex_unlock(&s3c_ac97.lock);
166 s3c_ac97.regs + S3C_AC97_GLBCTRL);
169 writel(0, s3c_ac97.regs + S3C_AC97_GLBCTRL);
177 stat = readl(s3c_ac97.regs + S3C_AC97_GLBSTAT) & 0x7;
181 writel(S3C_AC97_GLBCTRL_WARMRESET, s3c_ac97.regs + S3C_AC97_GLBCTRL);
184 writel(0, s3c_ac97.regs + S3C_AC97_GLBCTRL);
194 ac_glbstat = readl(s3c_ac97.regs + S3C_AC97_GLBSTAT);
198 ac_glbctrl = readl(s3c_ac97.regs + S3C_AC97_GLBCTRL);
200 writel(ac_glbctrl, s3c_ac97.regs + S3C_AC97_GLBCTRL);
202 complete(&s3c_ac97.done);
205 ac_glbctrl = readl(s3c_ac97.regs + S3C_AC97_GLBCTRL);
207 writel(ac_glbctrl, s3c_ac97.regs + S3C_AC97_GLBCTRL);
246 ac_glbctrl = readl(s3c_ac97.regs + S3C_AC97_GLBCTRL);
268 writel(ac_glbctrl, s3c_ac97.regs + S3C_AC97_GLBCTRL);
298 ac_glbctrl = readl(s3c_ac97.regs + S3C_AC97_GLBCTRL);
314 writel(ac_glbctrl, s3c_ac97.regs + S3C_AC97_GLBCTRL);
421 init_completion(&s3c_ac97.done);
422 mutex_init(&s3c_ac97.lock);
424 s3c_ac97.regs = ioremap(mem_res->start, resource_size(mem_res));
425 if (s3c_ac97.regs == NULL) {
431 s3c_ac97.ac97_clk = clk_get(&pdev->dev, "ac97");
432 if (IS_ERR(s3c_ac97.ac97_clk)) {
437 clk_enable(s3c_ac97.ac97_clk);
465 clk_disable(s3c_ac97.ac97_clk);
466 clk_put(s3c_ac97.ac97_clk);
468 iounmap(s3c_ac97.regs);
485 clk_disable(s3c_ac97.ac97_clk);
486 clk_put(s3c_ac97.ac97_clk);
488 iounmap(s3c_ac97.regs);