Lines Matching refs:omap_mcpdm_write
40 static inline void omap_mcpdm_write(u16 reg, u32 val)
97 omap_mcpdm_write(MCPDM_CTRL, ctrl);
109 omap_mcpdm_write(MCPDM_CTRL, ctrl);
125 omap_mcpdm_write(MCPDM_CTRL, ctrl);
141 omap_mcpdm_write(MCPDM_CTRL, ctrl);
160 omap_mcpdm_write(MCPDM_IRQENABLE_SET, irq_mask);
166 omap_mcpdm_write(MCPDM_FIFO_CTRL_UP, uplink->threshold);
169 omap_mcpdm_write(MCPDM_DMAENABLE_SET, DMA_UP_ENABLE);
179 omap_mcpdm_write(MCPDM_CTRL, ctrl);
200 omap_mcpdm_write(MCPDM_IRQENABLE_SET, irq_mask);
206 omap_mcpdm_write(MCPDM_FIFO_CTRL_DN, downlink->threshold);
209 omap_mcpdm_write(MCPDM_DMAENABLE_SET, DMA_DN_ENABLE);
219 omap_mcpdm_write(MCPDM_CTRL, ctrl);
237 omap_mcpdm_write(MCPDM_IRQENABLE_CLR, irq_mask);
240 omap_mcpdm_write(MCPDM_DMAENABLE_CLR, DMA_UP_ENABLE);
263 omap_mcpdm_write(MCPDM_IRQENABLE_CLR, irq_mask);
266 omap_mcpdm_write(MCPDM_DMAENABLE_CLR, DMA_DN_ENABLE);
284 omap_mcpdm_write(MCPDM_IRQSTATUS, irq_status);
344 omap_mcpdm_write(MCPDM_CTRL, 0x00);
400 omap_mcpdm_write(MCPDM_DN_OFFSET, offset);