Lines Matching defs:ssc_p
165 struct atmel_ssc_info *ssc_p = dev_id;
171 ssc_sr = (unsigned long)ssc_readl(ssc_p->ssc->regs, SR)
172 & (unsigned long)ssc_readl(ssc_p->ssc->regs, IMR);
180 for (i = 0; i < ARRAY_SIZE(ssc_p->dma_params); i++) {
181 dma_params = ssc_p->dma_params[i];
209 struct atmel_ssc_info *ssc_p = &ssc_info[rtd->dai->cpu_dai->id];
213 ssc_readl(ssc_p->ssc->regs, SR));
220 spin_lock_irq(&ssc_p->lock);
221 if (ssc_p->dir_mask & dir_mask) {
222 spin_unlock_irq(&ssc_p->lock);
225 ssc_p->dir_mask |= dir_mask;
226 spin_unlock_irq(&ssc_p->lock);
239 struct atmel_ssc_info *ssc_p = &ssc_info[rtd->dai->cpu_dai->id];
248 dma_params = ssc_p->dma_params[dir];
251 ssc_writel(ssc_p->ssc->regs, CR, dma_params->mask->ssc_disable);
254 ssc_readl(ssc_p->ssc->regs, SR));
258 ssc_p->dma_params[dir] = NULL;
263 spin_lock_irq(&ssc_p->lock);
264 ssc_p->dir_mask &= ~dir_mask;
265 if (!ssc_p->dir_mask) {
266 if (ssc_p->initialized) {
269 clk_disable(ssc_p->ssc->clk);
271 free_irq(ssc_p->ssc->irq, ssc_p);
272 ssc_p->initialized = 0;
276 ssc_writel(ssc_p->ssc->regs, CR, SSC_BIT(CR_SWRST));
278 ssc_p->cmr_div = ssc_p->tcmr_period = ssc_p->rcmr_period = 0;
280 spin_unlock_irq(&ssc_p->lock);
290 struct atmel_ssc_info *ssc_p = &ssc_info[cpu_dai->id];
292 ssc_p->daifmt = fmt;
302 struct atmel_ssc_info *ssc_p = &ssc_info[cpu_dai->id];
311 if (ssc_p->cmr_div == 0)
312 ssc_p->cmr_div = div;
314 if (div != ssc_p->cmr_div)
319 ssc_p->tcmr_period = div;
323 ssc_p->rcmr_period = div;
342 struct atmel_ssc_info *ssc_p = &ssc_info[id];
360 dma_params->ssc = ssc_p->ssc;
363 ssc_p->dma_params[dir] = dma_params;
404 if ((ssc_p->daifmt & SND_SOC_DAIFMT_FORMAT_MASK) == SND_SOC_DAIFMT_I2S
415 switch (ssc_p->daifmt
426 rcmr = SSC_BF(RCMR_PERIOD, ssc_p->rcmr_period)
441 tcmr = SSC_BF(TCMR_PERIOD, ssc_p->tcmr_period)
515 rcmr = SSC_BF(RCMR_PERIOD, ssc_p->rcmr_period)
530 tcmr = SSC_BF(TCMR_PERIOD, ssc_p->tcmr_period)
550 ssc_p->daifmt);
557 if (!ssc_p->initialized) {
561 clk_enable(ssc_p->ssc->clk);
564 ssc_writel(ssc_p->ssc->regs, CR, SSC_BIT(CR_SWRST));
566 ssc_writel(ssc_p->ssc->regs, PDC_RPR, 0);
567 ssc_writel(ssc_p->ssc->regs, PDC_RCR, 0);
568 ssc_writel(ssc_p->ssc->regs, PDC_RNPR, 0);
569 ssc_writel(ssc_p->ssc->regs, PDC_RNCR, 0);
571 ssc_writel(ssc_p->ssc->regs, PDC_TPR, 0);
572 ssc_writel(ssc_p->ssc->regs, PDC_TCR, 0);
573 ssc_writel(ssc_p->ssc->regs, PDC_TNPR, 0);
574 ssc_writel(ssc_p->ssc->regs, PDC_TNCR, 0);
576 ret = request_irq(ssc_p->ssc->irq, atmel_ssc_interrupt, 0,
577 ssc_p->name, ssc_p);
582 clk_disable(ssc_p->ssc->clk);
586 ssc_p->initialized = 1;
590 ssc_writel(ssc_p->ssc->regs, CMR, ssc_p->cmr_div);
593 ssc_writel(ssc_p->ssc->regs, RCMR, rcmr);
594 ssc_writel(ssc_p->ssc->regs, RFMR, rfmr);
597 ssc_writel(ssc_p->ssc->regs, TCMR, tcmr);
598 ssc_writel(ssc_p->ssc->regs, TFMR, tfmr);
609 struct atmel_ssc_info *ssc_p = &ssc_info[rtd->dai->cpu_dai->id];
618 dma_params = ssc_p->dma_params[dir];
620 ssc_writel(ssc_p->ssc->regs, CR, dma_params->mask->ssc_enable);
624 ssc_readl(ssc_p->ssc->regs, SR));
632 struct atmel_ssc_info *ssc_p;
637 ssc_p = &ssc_info[cpu_dai->id];
640 ssc_p->ssc_state.ssc_sr = ssc_readl(ssc_p->ssc->regs, SR);
641 ssc_writel(ssc_p->ssc->regs, CR, SSC_BIT(CR_TXDIS) | SSC_BIT(CR_RXDIS));
644 ssc_p->ssc_state.ssc_imr = ssc_readl(ssc_p->ssc->regs, IMR);
645 ssc_writel(ssc_p->ssc->regs, IDR, ssc_p->ssc_state.ssc_imr);
647 ssc_p->ssc_state.ssc_cmr = ssc_readl(ssc_p->ssc->regs, CMR);
648 ssc_p->ssc_state.ssc_rcmr = ssc_readl(ssc_p->ssc->regs, RCMR);
649 ssc_p->ssc_state.ssc_rfmr = ssc_readl(ssc_p->ssc->regs, RFMR);
650 ssc_p->ssc_state.ssc_tcmr = ssc_readl(ssc_p->ssc->regs, TCMR);
651 ssc_p->ssc_state.ssc_tfmr = ssc_readl(ssc_p->ssc->regs, TFMR);
660 struct atmel_ssc_info *ssc_p;
666 ssc_p = &ssc_info[cpu_dai->id];
669 ssc_writel(ssc_p->ssc->regs, TFMR, ssc_p->ssc_state.ssc_tfmr);
670 ssc_writel(ssc_p->ssc->regs, TCMR, ssc_p->ssc_state.ssc_tcmr);
671 ssc_writel(ssc_p->ssc->regs, RFMR, ssc_p->ssc_state.ssc_rfmr);
672 ssc_writel(ssc_p->ssc->regs, RCMR, ssc_p->ssc_state.ssc_rcmr);
673 ssc_writel(ssc_p->ssc->regs, CMR, ssc_p->ssc_state.ssc_cmr);
676 ssc_writel(ssc_p->ssc->regs, IER, ssc_p->ssc_state.ssc_imr);
681 (ssc_p->ssc_state.ssc_sr & SSC_BIT(SR_RXEN)) ? SSC_BIT(CR_RXEN) : 0;
683 (ssc_p->ssc_state.ssc_sr & SSC_BIT(SR_TXEN)) ? SSC_BIT(CR_TXEN) : 0;
684 ssc_writel(ssc_p->ssc->regs, CR, cr);