Lines Matching refs:control_register
447 u32 control_register; /* cached value */
976 hdsp->period_bytes = 1 << ((hdsp_decode_latency(hdsp->control_register) + 8));
1006 s->control_register |= (HDSP_AudioInterruptEnable | HDSP_Start);
1007 hdsp_write(s, HDSP_controlRegister, s->control_register);
1012 s->control_register &= ~(HDSP_Start | HDSP_AudioInterruptEnable);
1013 hdsp_write(s, HDSP_controlRegister, s->control_register);
1034 s->control_register &= ~HDSP_LatencyMask;
1035 s->control_register |= hdsp_encode_latency(n);
1037 hdsp_write(s, HDSP_controlRegister, s->control_register);
1076 if (!(hdsp->control_register & HDSP_ClockModeMaster)) {
1169 hdsp->control_register &= ~HDSP_FrequencyMask;
1170 hdsp->control_register |= rate_bits;
1171 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
1310 hmidi->hdsp->control_register |= HDSP_Midi1InterruptEnable;
1312 hmidi->hdsp->control_register |= HDSP_Midi0InterruptEnable;
1313 hdsp_write(hmidi->hdsp, HDSP_controlRegister, hmidi->hdsp->control_register);
1330 if (!(hdsp->control_register & ie)) {
1332 hdsp->control_register |= ie;
1335 hdsp->control_register &= ~ie;
1339 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
1567 hdsp->control_register &= ~(HDSP_SPDIFProfessional | HDSP_SPDIFNonAudio | HDSP_SPDIFEmphasis);
1568 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register |= val);
1596 return hdsp_decode_spdif_in(hdsp->control_register & HDSP_SPDIFInputMask);
1601 hdsp->control_register &= ~HDSP_SPDIFInputMask;
1602 hdsp->control_register |= hdsp_encode_spdif_in(in);
1603 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
1653 return (hdsp->control_register & HDSP_SPDIFOpticalOut) ? 1 : 0;
1659 hdsp->control_register |= HDSP_SPDIFOpticalOut;
1661 hdsp->control_register &= ~HDSP_SPDIFOpticalOut;
1662 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
1699 return (hdsp->control_register & HDSP_SPDIFProfessional) ? 1 : 0;
1705 hdsp->control_register |= HDSP_SPDIFProfessional;
1707 hdsp->control_register &= ~HDSP_SPDIFProfessional;
1708 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
1743 return (hdsp->control_register & HDSP_SPDIFEmphasis) ? 1 : 0;
1749 hdsp->control_register |= HDSP_SPDIFEmphasis;
1751 hdsp->control_register &= ~HDSP_SPDIFEmphasis;
1752 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
1787 return (hdsp->control_register & HDSP_SPDIFNonAudio) ? 1 : 0;
1793 hdsp->control_register |= HDSP_SPDIFNonAudio;
1795 hdsp->control_register &= ~HDSP_SPDIFNonAudio;
1796 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
1980 if (hdsp->control_register & HDSP_ClockModeMaster)
2019 if (hdsp->control_register & HDSP_ClockModeMaster) {
2054 hdsp->control_register &= ~HDSP_ClockModeMaster;
2055 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
2090 hdsp->control_register |= HDSP_ClockModeMaster;
2091 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
2179 switch (hdsp->control_register & HDSP_DAGainMask) {
2193 hdsp->control_register &= ~HDSP_DAGainMask;
2196 hdsp->control_register |= HDSP_DAGainHighGain;
2199 hdsp->control_register |= HDSP_DAGainPlus4dBu;
2202 hdsp->control_register |= HDSP_DAGainMinus10dBV;
2208 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
2264 switch (hdsp->control_register & HDSP_ADGainMask) {
2278 hdsp->control_register &= ~HDSP_ADGainMask;
2281 hdsp->control_register |= HDSP_ADGainMinus10dBV;
2284 hdsp->control_register |= HDSP_ADGainPlus4dBu;
2287 hdsp->control_register |= HDSP_ADGainLowGain;
2293 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
2349 switch (hdsp->control_register & HDSP_PhoneGainMask) {
2363 hdsp->control_register &= ~HDSP_PhoneGainMask;
2366 hdsp->control_register |= HDSP_PhoneGain0dB;
2369 hdsp->control_register |= HDSP_PhoneGainMinus6dB;
2372 hdsp->control_register |= HDSP_PhoneGainMinus12dB;
2378 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
2434 if (hdsp->control_register & HDSP_XLRBreakoutCable)
2442 hdsp->control_register |= HDSP_XLRBreakoutCable;
2444 hdsp->control_register &= ~HDSP_XLRBreakoutCable;
2445 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
2490 if (hdsp->control_register & HDSP_AnalogExtensionBoard)
2498 hdsp->control_register |= HDSP_AnalogExtensionBoard;
2500 hdsp->control_register &= ~HDSP_AnalogExtensionBoard;
2501 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
2546 switch (hdsp->control_register & HDSP_SyncRefMask) {
2567 hdsp->control_register &= ~HDSP_SyncRefMask;
2570 hdsp->control_register &= ~HDSP_SyncRefMask; /* clear SyncRef bits */
2573 hdsp->control_register |= HDSP_SyncRef_ADAT2;
2576 hdsp->control_register |= HDSP_SyncRef_ADAT3;
2579 hdsp->control_register |= HDSP_SyncRef_SPDIF;
2582 hdsp->control_register |= HDSP_SyncRef_WORD;
2585 hdsp->control_register |= HDSP_SyncRef_ADAT_SYNC;
2590 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
2731 return (hdsp->control_register & HDSP_LineOut) ? 1 : 0;
2737 hdsp->control_register |= HDSP_LineOut;
2739 hdsp->control_register &= ~HDSP_LineOut;
2740 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
3304 snd_iprintf(buffer, "Control register: 0x%x\n", hdsp->control_register);
3347 x = 1 << (6 + hdsp_decode_latency(hdsp->control_register & HDSP_LatencyMask));
3352 snd_iprintf(buffer, "Line out: %s\n", (hdsp->control_register & HDSP_LineOut) ? "on" : "off");
3479 if (hdsp->control_register & HDSP_SPDIFOpticalOut)
3484 if (hdsp->control_register & HDSP_SPDIFProfessional)
3489 if (hdsp->control_register & HDSP_SPDIFEmphasis)
3494 if (hdsp->control_register & HDSP_SPDIFNonAudio)
3596 if (hdsp->control_register & HDSP_AnalogExtensionBoard)
3665 hdsp->control_register = HDSP_ClockModeMaster |
3671 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
3698 hdsp->control_register |= (HDSP_DAGainPlus4dBu | HDSP_ADGainPlus4dBu | HDSP_PhoneGain0dB);
3699 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
3759 hdsp->control_register &= ~HDSP_Midi0InterruptEnable;
3760 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
3770 hdsp->control_register &= ~HDSP_Midi1InterruptEnable;
3771 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
3898 hdsp->control_register &= ~(HDSP_SPDIFProfessional | HDSP_SPDIFNonAudio | HDSP_SPDIFEmphasis);
3899 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register |= hdsp->creg_spdif_stream);
5009 hdsp->control_register = 0;
5137 hdsp->control_register &= ~(HDSP_Start|HDSP_AudioInterruptEnable|HDSP_Midi0InterruptEnable|HDSP_Midi1InterruptEnable);
5138 hdsp_write (hdsp, HDSP_controlRegister, hdsp->control_register);