Lines Matching refs:wcreg
208 u32 wcreg; /* cached write control register value */
243 #define RME96_ISPLAYING(rme96) ((rme96)->wcreg & RME96_WCR_START)
244 #define RME96_ISRECORDING(rme96) ((rme96)->wcreg & RME96_WCR_START_2)
503 writel(rme96->wcreg | RME96_WCR_PD,
505 writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
511 return ((rme96->wcreg >> RME96_WCR_BITPOS_MONITOR_0) & 1) +
512 (((rme96->wcreg >> RME96_WCR_BITPOS_MONITOR_1) & 1) << 1);
520 rme96->wcreg |= RME96_WCR_MONITOR_0;
522 rme96->wcreg &= ~RME96_WCR_MONITOR_0;
525 rme96->wcreg |= RME96_WCR_MONITOR_1;
527 rme96->wcreg &= ~RME96_WCR_MONITOR_1;
529 writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
536 return ((rme96->wcreg >> RME96_WCR_BITPOS_GAIN_0) & 1) +
537 (((rme96->wcreg >> RME96_WCR_BITPOS_GAIN_1) & 1) << 1);
546 rme96->wcreg = (rme96->wcreg & ~RME96_WCR_GAIN_0) &
550 rme96->wcreg = (rme96->wcreg | RME96_WCR_GAIN_0) &
554 rme96->wcreg = (rme96->wcreg & ~RME96_WCR_GAIN_0) |
558 rme96->wcreg = (rme96->wcreg | RME96_WCR_GAIN_0) |
564 writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
636 if (!(rme96->wcreg & RME96_WCR_MASTER) &&
643 rate = ((rme96->wcreg >> RME96_WCR_BITPOS_FREQ_0) & 1) +
644 (((rme96->wcreg >> RME96_WCR_BITPOS_FREQ_1) & 1) << 1);
658 return (rme96->wcreg & RME96_WCR_DS) ? rate << 1 : rate;
667 ds = rme96->wcreg & RME96_WCR_DS;
670 rme96->wcreg &= ~RME96_WCR_DS;
671 rme96->wcreg = (rme96->wcreg | RME96_WCR_FREQ_0) &
675 rme96->wcreg &= ~RME96_WCR_DS;
676 rme96->wcreg = (rme96->wcreg | RME96_WCR_FREQ_1) &
680 rme96->wcreg &= ~RME96_WCR_DS;
681 rme96->wcreg = (rme96->wcreg | RME96_WCR_FREQ_0) |
685 rme96->wcreg |= RME96_WCR_DS;
686 rme96->wcreg = (rme96->wcreg | RME96_WCR_FREQ_0) &
690 rme96->wcreg |= RME96_WCR_DS;
691 rme96->wcreg = (rme96->wcreg | RME96_WCR_FREQ_1) &
695 rme96->wcreg |= RME96_WCR_DS;
696 rme96->wcreg = (rme96->wcreg | RME96_WCR_FREQ_0) |
702 if ((!ds && rme96->wcreg & RME96_WCR_DS) ||
703 (ds && !(rme96->wcreg & RME96_WCR_DS)))
708 writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
762 rme96->wcreg &= ~RME96_WCR_MASTER;
767 rme96->wcreg |= RME96_WCR_MASTER;
772 rme96->wcreg |= RME96_WCR_MASTER;
778 writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
789 return (rme96->wcreg & RME96_WCR_MASTER) ? RME96_CLOCKMODE_MASTER :
801 rme96->wcreg = (rme96->wcreg & ~RME96_WCR_INP_0) &
805 rme96->wcreg = (rme96->wcreg | RME96_WCR_INP_0) &
809 rme96->wcreg = (rme96->wcreg & ~RME96_WCR_INP_0) |
821 rme96->wcreg = (rme96->wcreg | RME96_WCR_INP_0) |
850 writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
860 return ((rme96->wcreg >> RME96_WCR_BITPOS_INP_0) & 1) +
861 (((rme96->wcreg >> RME96_WCR_BITPOS_INP_1) & 1) << 1);
878 frlog += (rme96->wcreg & RME96_WCR_MODE24) ? 2 : 1;
881 frlog += (rme96->wcreg & RME96_WCR_MODE24_2) ? 2 : 1;
892 rme96->wcreg &= ~RME96_WCR_MODE24;
895 rme96->wcreg |= RME96_WCR_MODE24;
900 writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
910 rme96->wcreg &= ~RME96_WCR_MODE24_2;
913 rme96->wcreg |= RME96_WCR_MODE24_2;
918 writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
928 rme96->wcreg &= ~RME96_WCR_ISEL;
931 rme96->wcreg |= RME96_WCR_ISEL;
937 rme96->wcreg &= ~RME96_WCR_IDIS;
938 writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
955 if (!(rme96->wcreg & RME96_WCR_MASTER) &&
985 if ((rme96->wcreg & RME96_WCR_ADAT) == 0) {
986 rme96->wcreg &= ~(RME96_WCR_PRO | RME96_WCR_DOLBY | RME96_WCR_EMP);
987 writel(rme96->wcreg |= rme96->wcreg_spdif_stream, rme96->iobase + RME96_IO_CONTROL_REGISTER);
1056 rme96->wcreg |= RME96_WCR_START;
1057 writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
1068 rme96->wcreg |= RME96_WCR_START_2;
1069 writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
1083 rme96->wcreg &= ~RME96_WCR_START;
1084 writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
1094 rme96->wcreg &= ~RME96_WCR_START_2;
1095 writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
1164 rme96->wcreg &= ~RME96_WCR_ADAT;
1165 writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
1170 if (!(rme96->wcreg & RME96_WCR_MASTER) &&
1231 rme96->wcreg |= RME96_WCR_ADAT;
1232 writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
1237 if (!(rme96->wcreg & RME96_WCR_MASTER) &&
1296 spdif = (rme96->wcreg & RME96_WCR_ADAT) == 0;
1614 rme96->wcreg =
1622 writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
1672 if (rme96->wcreg & RME96_WCR_IDIS) {
1675 } else if (rme96->wcreg & RME96_WCR_ISEL) {
1709 if (rme96->wcreg & RME96_WCR_MODE24_2) {
1716 if (rme96->wcreg & RME96_WCR_SEL) {
1723 if (rme96->wcreg & RME96_WCR_MODE24) {
1730 } else if (rme96->wcreg & RME96_WCR_MASTER) {
1739 if (rme96->wcreg & RME96_WCR_PRO) {
1744 if (rme96->wcreg & RME96_WCR_EMP) {
1749 if (rme96->wcreg & RME96_WCR_DOLBY) {
1810 ucontrol->value.integer.value[0] = rme96->wcreg & RME96_WCR_SEL ? 0 : 1;
1823 val = (rme96->wcreg & ~RME96_WCR_SEL) | val;
1824 change = val != rme96->wcreg;
1825 rme96->wcreg = val;
2143 rme96->wcreg &= ~(RME96_WCR_PRO | RME96_WCR_DOLBY | RME96_WCR_EMP);
2144 rme96->wcreg |= val;
2145 writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);