Lines Matching refs:rmh
56 struct pcxhr_rmh rmh;
58 pcxhr_init_rmh(&rmh, CMD_ACCESS_IO_WRITE);
60 rmh.cmd[0] |= IO_NUM_REG_IN_ANA_LEVEL;
61 rmh.cmd[2] = chip->analog_capture_volume[channel];
63 rmh.cmd[0] |= IO_NUM_REG_OUT_ANA_LEVEL;
69 rmh.cmd[2] = PCXHR_LINE_PLAYBACK_LEVEL_MAX - vol;
71 rmh.cmd[1] = 1 << ((2 * chip->chip_idx) + channel); /* audio mask */
72 rmh.cmd_len = 3;
73 err = pcxhr_send_msg(chip->mgr, &rmh);
261 struct pcxhr_rmh rmh;
274 pcxhr_init_rmh(&rmh, CMD_STREAM_OUT_LEVEL_ADJUST);
276 pcxhr_set_pipe_cmd_params(&rmh, 0, pipe->first_audio, 0, 1<<idx);
278 rmh.cmd[0] |= MORE_THAN_ONE_STREAM_LEVEL;
279 rmh.cmd[2] = VALID_STREAM_PAN_LEVEL_MASK | VALID_STREAM_LEVEL_1_MASK;
280 rmh.cmd[2] |= (left << 10);
281 rmh.cmd[3] = VALID_STREAM_PAN_LEVEL_MASK | VALID_STREAM_LEVEL_2_MASK;
282 rmh.cmd[3] |= right;
283 rmh.cmd_len = 4;
285 err = pcxhr_send_msg(chip->mgr, &rmh);
305 struct pcxhr_rmh rmh;
313 pcxhr_init_rmh(&rmh, CMD_AUDIO_LEVEL_ADJUST);
315 pcxhr_set_pipe_cmd_params(&rmh, capture, 0, 0,
320 rmh.cmd[0] |= VALID_AUDIO_IO_DIGITAL_LEVEL;
323 rmh.cmd[2] = chip->digital_capture_volume[channel];
325 rmh.cmd[0] |= VALID_AUDIO_IO_MONITOR_LEVEL |
330 rmh.cmd[2] = chip->monitoring_volume[channel] << 10;
332 rmh.cmd[2] |= AUDIO_IO_HAS_MUTE_MONITOR_1;
334 rmh.cmd_len = 3;
336 err = pcxhr_send_msg(chip->mgr, &rmh);
584 struct pcxhr_rmh rmh;
605 pcxhr_init_rmh(&rmh, CMD_RESYNC_AUDIO_INPUTS);
606 rmh.cmd[0] |= (1 << chip->chip_idx);
607 err = pcxhr_send_msg(chip->mgr, &rmh);
620 pcxhr_init_rmh(&rmh, CMD_ACCESS_IO_WRITE);
621 rmh.cmd_len = 2;
622 rmh.cmd[0] |= IO_NUM_REG_CONFIG_SRC;
623 rmh.cmd[1] = src_config;
624 err = pcxhr_send_msg(chip->mgr, &rmh);
630 pcxhr_init_rmh(&rmh, CMD_ACCESS_IO_WRITE);
631 rmh.cmd_len = 3;
632 rmh.cmd[0] |= IO_NUM_UER_CHIP_REG;
633 rmh.cmd[1] = codec;
634 rmh.cmd[2] = ((CS8420_DATA_FLOW_CTL & CHIP_SIG_AND_MAP_SPI) |
636 err = pcxhr_send_msg(chip->mgr, &rmh);
639 rmh.cmd[2] = ((CS8420_CLOCK_SRC_CTL & CHIP_SIG_AND_MAP_SPI) |
641 err = pcxhr_send_msg(chip->mgr, &rmh);
881 struct pcxhr_rmh rmh;
883 pcxhr_init_rmh(&rmh, CMD_ACCESS_IO_READ);
884 rmh.cmd[0] |= IO_NUM_UER_CHIP_REG;
887 case 0: rmh.cmd[1] = CS8420_01_CS; break;
888 case 1: rmh.cmd[1] = CS8420_23_CS; break;
889 case 2: rmh.cmd[1] = CS8420_45_CS; break;
890 case 3: rmh.cmd[1] = CS8420_67_CS; break;
895 case 0: rmh.cmd[2] = CS8416_CSB0; break;
896 case 1: rmh.cmd[2] = CS8416_CSB1; break;
897 case 2: rmh.cmd[2] = CS8416_CSB2; break;
898 case 3: rmh.cmd[2] = CS8416_CSB3; break;
899 case 4: rmh.cmd[2] = CS8416_CSB4; break;
905 case 0: rmh.cmd[2] = CS8420_CSB0; break;
906 case 1: rmh.cmd[2] = CS8420_CSB1; break;
907 case 2: rmh.cmd[2] = CS8420_CSB2; break;
908 case 3: rmh.cmd[2] = CS8420_CSB3; break;
909 case 4: rmh.cmd[2] = CS8420_CSB4; break;
914 rmh.cmd[1] &= 0x0fffff;
916 rmh.cmd[2] &= CHIP_SIG_AND_MAP_SPI;
917 rmh.cmd_len = 3;
918 err = pcxhr_send_msg(chip->mgr, &rmh);
923 temp = (unsigned char)rmh.stat[1];
929 if (rmh.stat[1] & (1 << i))
981 struct pcxhr_rmh rmh;
991 pcxhr_init_rmh(&rmh, CMD_ACCESS_IO_WRITE);
992 rmh.cmd[0] |= IO_NUM_REG_CUER;
993 rmh.cmd[1] = cmd;
994 rmh.cmd_len = 2;
997 err = pcxhr_send_msg(chip->mgr, &rmh);