Lines Matching defs:chip
31 static int write_control_reg(struct echoaudio *chip, u32 value, char force);
32 static int set_input_clock(struct echoaudio *chip, u16 clock);
33 static int set_professional_spdif(struct echoaudio *chip, char prof);
34 static int set_digital_mode(struct echoaudio *chip, u8 mode);
35 static int load_asic_generic(struct echoaudio *chip, u32 cmd, short asic);
36 static int check_asic_status(struct echoaudio *chip);
39 static int init_hw(struct echoaudio *chip, u16 device_id, u16 subdevice_id)
47 if ((err = init_dsp_comm_page(chip))) {
52 chip->device_id = device_id;
53 chip->subdevice_id = subdevice_id;
54 chip->bad_board = TRUE;
55 chip->has_midi = TRUE;
56 chip->dsp_code_to_load = FW_LAYLA24_DSP;
57 chip->input_clock_types =
60 chip->digital_modes =
65 if ((err = load_firmware(chip)) < 0)
67 chip->bad_board = FALSE;
69 if ((err = init_line_levels(chip)) < 0)
78 static int set_mixer_defaults(struct echoaudio *chip)
80 chip->digital_mode = DIGITAL_MODE_SPDIF_RCA;
81 chip->professional_spdif = FALSE;
82 chip->digital_in_automute = TRUE;
83 return init_line_levels(chip);
88 static u32 detect_input_clocks(const struct echoaudio *chip)
93 clocks_from_dsp = le32_to_cpu(chip->comm_page->status_clocks);
113 static int load_asic(struct echoaudio *chip)
117 if (chip->asic_loaded)
126 err = load_asic_generic(chip, DSP_FNC_LOAD_LAYLA24_PCI_CARD_ASIC,
131 chip->asic_code = FW_LAYLA24_2S_ASIC;
137 err = load_asic_generic(chip, DSP_FNC_LOAD_LAYLA24_EXTERNAL_ASIC,
146 err = check_asic_status(chip);
151 err = write_control_reg(chip, GML_CONVERTER_ENABLE | GML_48KHZ,
160 static int set_sample_rate(struct echoaudio *chip, u32 rate)
165 chip->digital_mode == DIGITAL_MODE_ADAT))
169 if (chip->input_clock != ECHO_CLOCK_INTERNAL) {
173 chip->comm_page->sample_rate = cpu_to_le32(rate);
174 chip->sample_rate = rate;
179 control_reg = le32_to_cpu(chip->comm_page->control_register);
230 if (wait_handshake(chip))
233 chip->comm_page->sample_rate =
236 clear_handshake(chip);
237 send_vector(chip, DSP_VC_SET_LAYLA24_FREQUENCY_REG);
242 chip->comm_page->sample_rate = cpu_to_le32(rate); /* ignored by the DSP ? */
243 chip->sample_rate = rate;
246 return write_control_reg(chip, control_reg, FALSE);
251 static int set_input_clock(struct echoaudio *chip, u16 clock)
256 control_reg = le32_to_cpu(chip->comm_page->control_register) &
258 clocks_from_dsp = le32_to_cpu(chip->comm_page->status_clocks);
264 chip->input_clock = ECHO_CLOCK_INTERNAL;
265 return set_sample_rate(chip, chip->sample_rate);
267 if (chip->digital_mode == DIGITAL_MODE_ADAT)
283 if (chip->digital_mode != DIGITAL_MODE_ADAT)
294 chip->input_clock = clock;
295 return write_control_reg(chip, control_reg, TRUE);
303 static int switch_asic(struct echoaudio *chip, short asic)
308 if (asic != chip->asic_code) {
309 monitors = kmemdup(chip->comm_page->monitors,
314 memset(chip->comm_page->monitors, ECHOGAIN_MUTED,
318 if (load_asic_generic(chip, DSP_FNC_LOAD_LAYLA24_EXTERNAL_ASIC,
320 memcpy(chip->comm_page->monitors, monitors,
325 chip->asic_code = asic;
326 memcpy(chip->comm_page->monitors, monitors, MONITOR_ARRAY_SIZE);
335 static int dsp_set_digital_mode(struct echoaudio *chip, u8 mode)
346 if (chip->input_clock == ECHO_CLOCK_ADAT)
351 if (chip->input_clock == ECHO_CLOCK_SPDIF)
361 chip->sample_rate = 48000;
362 spin_lock_irq(&chip->lock);
363 set_input_clock(chip, ECHO_CLOCK_INTERNAL);
364 spin_unlock_irq(&chip->lock);
368 if (switch_asic(chip, asic) < 0)
371 spin_lock_irq(&chip->lock);
374 control_reg = le32_to_cpu(chip->comm_page->control_register);
390 err = write_control_reg(chip, control_reg, TRUE);
391 spin_unlock_irq(&chip->lock);
394 chip->digital_mode = mode;