Lines Matching defs:BA0_CLKCR1
221 #define BA0_CLKCR1 0x0400 /* Clock Control Register 1 */
1310 snd_cs4281_pokeBA0(chip, BA0_CLKCR1, 0);
1456 snd_cs4281_pokeBA0(chip, BA0_CLKCR1, 0);
1486 snd_cs4281_pokeBA0(chip, BA0_CLKCR1, BA0_CLKCR1_DLLP);
1488 snd_cs4281_pokeBA0(chip, BA0_CLKCR1, BA0_CLKCR1_SWCE | BA0_CLKCR1_DLLP);
1499 if (snd_cs4281_peekBA0(chip, BA0_CLKCR1) & BA0_CLKCR1_DLLRDY)
2011 ulCLK = snd_cs4281_peekBA0(chip, BA0_CLKCR1);
2013 snd_cs4281_pokeBA0(chip, BA0_CLKCR1, ulCLK);
2030 snd_cs4281_pokeBA0(chip, BA0_CLKCR1, 0);
2035 ulCLK = snd_cs4281_peekBA0(chip, BA0_CLKCR1);
2037 snd_cs4281_pokeBA0(chip, BA0_CLKCR1, ulCLK);
2062 ulCLK = snd_cs4281_peekBA0(chip, BA0_CLKCR1);
2064 snd_cs4281_pokeBA0(chip, BA0_CLKCR1, ulCLK);
2076 ulCLK = snd_cs4281_peekBA0(chip, BA0_CLKCR1);
2078 snd_cs4281_pokeBA0(chip, BA0_CLKCR1, ulCLK);