Lines Matching refs:dma
934 stream_t *dma = &vortex->dma_adb[adbdma];
937 dma->dma_ctrl);
942 stream_t *dma = &vortex->dma_adb[adbdma];
946 dma->period_real = dma->period_virt = sb;
953 stream_t *dma = &vortex->dma_adb[adbdma];
955 dma->period_bytes = psize;
956 dma->nr_periods = count;
958 dma->cfg0 = 0;
959 dma->cfg1 = 0;
964 dma->cfg1 |= 0x88000000 | 0x44000000 | 0x30000000 | (psize - 1);
967 snd_pcm_sgbuf_get_addr(dma->substream, psize * 3));
970 dma->cfg0 |= 0x12000000;
971 dma->cfg1 |= 0x80000000 | 0x40000000 | ((psize - 1) << 0xc);
974 snd_pcm_sgbuf_get_addr(dma->substream, psize * 2));
977 dma->cfg0 |= 0x88000000 | 0x44000000 | 0x10000000 | (psize - 1);
980 snd_pcm_sgbuf_get_addr(dma->substream, psize));
983 dma->cfg0 |= 0x80000000 | 0x40000000 | ((psize - 1) << 0xc);
986 snd_pcm_sgbuf_get_addr(dma->substream, 0));
991 dma->cfg0, dma->cfg1);
993 hwwrite(vortex->mmio, VORTEX_ADBDMA_BUFCFG0 + (adbdma << 3), dma->cfg0);
994 hwwrite(vortex->mmio, VORTEX_ADBDMA_BUFCFG1 + (adbdma << 3), dma->cfg1);
1004 stream_t *dma = &vortex->dma_adb[adbdma];
1006 dma->dma_unknown = d;
1007 dma->dma_ctrl =
1008 ((offset & OFFSET_MASK) | (dma->dma_ctrl & ~OFFSET_MASK));
1010 dma->dma_ctrl =
1011 (dma->dma_ctrl & ~IE_MASK) | ((ie << IE_SHIFT) & IE_MASK);
1013 dma->dma_ctrl =
1014 (dma->dma_ctrl & ~DIR_MASK) | ((dir << DIR_SHIFT) & DIR_MASK);
1015 dma->dma_ctrl =
1016 (dma->dma_ctrl & ~FMT_MASK) | ((fmt << FMT_SHIFT) & FMT_MASK);
1019 dma->dma_ctrl);
1025 stream_t *dma = &vortex->dma_adb[adbdma];
1031 if (dma->nr_periods >= 4)
1032 delta = (page - dma->period_real) & 3;
1034 delta = (page - dma->period_real);
1036 delta += dma->nr_periods;
1042 if (dma->nr_periods > 4) {
1045 p = dma->period_virt + i + 4;
1046 if (p >= dma->nr_periods)
1047 p -= dma->nr_periods;
1049 pp = dma->period_real + i;
1052 //hwwrite(vortex->mmio, VORTEX_ADBDMA_BUFBASE+(((adbdma << 2)+pp) << 2), dma->table[p].addr);
1055 snd_pcm_sgbuf_get_addr(dma->substream,
1056 dma->period_bytes * p));
1062 dma->period_virt += delta;
1063 dma->period_real = page;
1064 if (dma->period_virt >= dma->nr_periods)
1065 dma->period_virt -= dma->nr_periods;
1068 adbdma, dma->period_virt, dma->period_real, delta);
1075 stream_t *dma = &vortex->dma_adb[adbdma];
1079 for (i=0 ; i < 4 && i < dma->nr_periods; i++) {
1081 p = dma->period_virt + i;
1082 if (p >= dma->nr_periods)
1083 p -= dma->nr_periods;
1085 pp = dma->period_real + i;
1086 if (dma->nr_periods < 4) {
1087 if (pp >= dma->nr_periods)
1088 pp -= dma->nr_periods;
1096 snd_pcm_sgbuf_get_addr(dma->substream,
1097 dma->period_bytes * p));
1105 stream_t *dma = &vortex->dma_adb[adbdma];
1109 temp = (dma->period_virt * dma->period_bytes) + (temp & (dma->period_bytes - 1));
1116 stream_t *dma = &vortex->dma_adb[adbdma];
1118 switch (dma->fifo_status) {
1121 dma->fifo_enabled ? 1 : 0);
1126 dma->dma_ctrl);
1127 vortex_fifo_setadbctrl(vortex, adbdma, dma->dma_unknown,
1129 dma->fifo_enabled ? 1 : 0, 0);
1132 vortex_fifo_setadbctrl(vortex, adbdma, dma->dma_unknown,
1134 dma->fifo_enabled ? 1 : 0, 0);
1137 dma->fifo_status = FIFO_START;
1142 stream_t *dma = &vortex->dma_adb[adbdma];
1145 switch (dma->fifo_status) {
1148 dma->dma_ctrl);
1149 vortex_fifo_setadbctrl(vortex, adbdma, dma->dma_unknown,
1151 dma->fifo_enabled ? 1 : 0, 0);
1154 vortex_fifo_setadbctrl(vortex, adbdma, dma->dma_unknown,
1156 dma->fifo_enabled ? 1 : 0, 0);
1159 dma->fifo_status = FIFO_START;
1164 stream_t *dma = &vortex->dma_adb[adbdma];
1167 switch (dma->fifo_status) {
1169 vortex_fifo_setadbctrl(vortex, adbdma, dma->dma_unknown,
1174 dma->dma_ctrl);
1175 vortex_fifo_setadbctrl(vortex, adbdma, dma->dma_unknown,
1179 dma->fifo_status = FIFO_PAUSE;
1188 stream_t *dma = &vortex->dma_wt[wtdma];
1190 hwwrite(vortex->mmio, VORTEX_WTDMA_CTRL + (wtdma << 2), dma->dma_ctrl);
1195 stream_t *dma = &vortex->dma_wt[wtdma];
1199 dma->period_real = dma->period_virt = sb;
1206 stream_t *dma = &vortex->dma_wt[wtdma];
1208 dma->period_bytes = psize;
1209 dma->nr_periods = count;
1211 dma->cfg0 = 0;
1212 dma->cfg1 = 0;
1217 dma->cfg1 |= 0x88000000 | 0x44000000 | 0x30000000 | (psize-1);
1219 snd_pcm_sgbuf_get_addr(dma->substream, psize * 3));
1222 dma->cfg0 |= 0x12000000;
1223 dma->cfg1 |= 0x80000000 | 0x40000000 | ((psize-1) << 0xc);
1225 snd_pcm_sgbuf_get_addr(dma->substream, psize * 2));
1228 dma->cfg0 |= 0x88000000 | 0x44000000 | 0x10000000 | (psize-1);
1230 snd_pcm_sgbuf_get_addr(dma->substream, psize));
1233 dma->cfg0 |= 0x80000000 | 0x40000000 | ((psize-1) << 0xc);
1235 snd_pcm_sgbuf_get_addr(dma->substream, 0));
1238 hwwrite(vortex->mmio, VORTEX_WTDMA_BUFCFG0 + (wtdma << 3), dma->cfg0);
1239 hwwrite(vortex->mmio, VORTEX_WTDMA_BUFCFG1 + (wtdma << 3), dma->cfg1);
1249 stream_t *dma = &vortex->dma_wt[wtdma];
1251 //dma->this_08 = e;
1252 dma->dma_unknown = d;
1253 dma->dma_ctrl = 0;
1254 dma->dma_ctrl =
1255 ((offset & OFFSET_MASK) | (dma->dma_ctrl & ~OFFSET_MASK));
1257 dma->dma_ctrl =
1258 (dma->dma_ctrl & ~IE_MASK) | ((ie << IE_SHIFT) & IE_MASK);
1260 dma->dma_ctrl |= (1 << DIR_SHIFT);
1262 dma->dma_ctrl =
1263 (dma->dma_ctrl & FMT_MASK) | ((fmt << FMT_SHIFT) & FMT_MASK);
1265 hwwrite(vortex->mmio, VORTEX_WTDMA_CTRL + (wtdma << 2), dma->dma_ctrl);
1270 stream_t *dma = &vortex->dma_wt[wtdma];
1277 if (dma->nr_periods >= 4)
1278 delta = (page - dma->period_real) & 3;
1280 delta = (page - dma->period_real);
1282 delta += dma->nr_periods;
1288 if (dma->nr_periods > 4) {
1291 p = dma->period_virt + i + 4;
1292 if (p >= dma->nr_periods)
1293 p -= dma->nr_periods;
1295 pp = dma->period_real + i;
1301 snd_pcm_sgbuf_get_addr(dma->substream,
1302 dma->period_bytes * p));
1308 dma->period_virt += delta;
1309 if (dma->period_virt >= dma->nr_periods)
1310 dma->period_virt -= dma->nr_periods;
1311 dma->period_real = page;
1315 dma->period_virt, delta);
1322 stream_t *dma = &vortex->dma_wt[wtdma];
1326 temp = (dma->period_virt * dma->period_bytes) + (temp & (dma->period_bytes - 1));
1332 stream_t *dma = &vortex->dma_wt[wtdma];
1335 switch (dma->fifo_status) {
1338 dma->fifo_enabled ? 1 : 0);
1343 dma->dma_ctrl);
1344 vortex_fifo_setwtctrl(vortex, wtdma, dma->dma_unknown,
1346 dma->fifo_enabled ? 1 : 0, 0);
1349 vortex_fifo_setwtctrl(vortex, wtdma, dma->dma_unknown,
1351 dma->fifo_enabled ? 1 : 0, 0);
1354 dma->fifo_status = FIFO_START;
1359 stream_t *dma = &vortex->dma_wt[wtdma];
1362 switch (dma->fifo_status) {
1365 dma->dma_ctrl);
1366 vortex_fifo_setwtctrl(vortex, wtdma, dma->dma_unknown,
1368 dma->fifo_enabled ? 1 : 0, 0);
1371 vortex_fifo_setwtctrl(vortex, wtdma, dma->dma_unknown,
1373 dma->fifo_enabled ? 1 : 0, 0);
1376 dma->fifo_status = FIFO_START;
1381 stream_t *dma = &vortex->dma_wt[wtdma];
1384 switch (dma->fifo_status) {
1386 vortex_fifo_setwtctrl(vortex, wtdma, dma->dma_unknown,
1391 dma->dma_ctrl);
1392 vortex_fifo_setwtctrl(vortex, wtdma, dma->dma_unknown,
1396 dma->fifo_status = FIFO_PAUSE;
1401 stream_t *dma = &vortex->dma_wt[wtdma];
1404 if (dma->fifo_status == FIFO_START)
1405 vortex_fifo_setwtctrl(vortex, wtdma, dma->dma_unknown,
1407 else if (dma->fifo_status == FIFO_STOP)
1409 dma->fifo_status = FIFO_STOP;
1410 dma->fifo_enabled = 0;
1738 a DMA resource (root of all other resources of a dma channel).
1790 vortex_adb_allocroute(vortex_t * vortex, int dma, int nr_ch, int dir, int type);
1841 Allocate nr_ch pcm audio routes if dma < 0. If dma >= 0, existing routes
1843 dma: DMA engine routes to be deallocated when dma >= 0.
1847 Return: Return allocated DMA or same DMA passed as "dma" when dma >= 0.
1850 vortex_adb_allocroute(vortex_t * vortex, int dma, int nr_ch, int dir, int type)
1859 if (dma >= 0) {
1862 vortex->dma_adb[dma].resources, en,
1866 if ((dma =
1872 stream = &vortex->dma_adb[dma];
1873 stream->dma = dma;
1937 dma,
1959 dma,
1963 //vortex_route(vortex, en, 0x11, dma, ADB_XTALKIN(i?9:4));
1968 ADB_DMA(stream->dma),
1994 ADB_DMA(stream->dma),
2042 src[0], dma);
2050 src[1], dma);
2053 vortex->dma_adb[dma].nr_ch = nr_ch;
2055 return dma;
2143 printk(KERN_ERR "vortex: IRQ dma error\n");