Lines Matching defs:phw
481 struct hpi_hw_obj *phw = (struct hpi_hw_obj *)pao->priv;
482 phw->ado[dsp_index].pa_parent_adapter = pao;
495 struct hpi_hw_obj *phw;
501 phw = (struct hpi_hw_obj *)pao->priv;
504 hpi_free_control_cache(phw->p_cache);
507 kfree(phw);
520 struct hpi_hw_obj *phw = (struct hpi_hw_obj *)pao->priv;
528 phw->dw2040_HPICSR = pao->pci.ap_mem_base[0];
529 phw->dw2040_HPIDSP = pao->pci.ap_mem_base[1];
530 HPI_DEBUG_LOG(VERBOSE, "csr %p, dsp %p\n", phw->dw2040_HPICSR,
531 phw->dw2040_HPIDSP);
535 phw->ado[dsp_index].prHPI_control =
536 phw->dw2040_HPIDSP + (CONTROL +
539 phw->ado[dsp_index].prHPI_address =
540 phw->dw2040_HPIDSP + (ADDRESS +
542 phw->ado[dsp_index].prHPI_data =
543 phw->dw2040_HPIDSP + (DATA + DSP_SPACING * dsp_index);
545 phw->ado[dsp_index].prHPI_data_auto_inc =
546 phw->dw2040_HPIDSP + (DATA_AUTOINC +
550 phw->ado[dsp_index].prHPI_control,
551 phw->ado[dsp_index].prHPI_address,
552 phw->ado[dsp_index].prHPI_data,
553 phw->ado[dsp_index].prHPI_data_auto_inc);
555 phw->ado[dsp_index].pa_parent_adapter = pao;
558 phw->pCI2040HPI_error_count = 0;
564 phw->num_dsp = 1;
572 phw->message_buffer_address_on_dsp = 0L;
573 phw->response_buffer_address_on_dsp = 0L;
600 if (phw->num_dsp == 2) {
610 memset(&phw->control_cache[0], 0,
615 hpi_read_word(&phw->ado[0],
619 hpi_read_word(&phw->ado[0],
623 phw->p_cache =
626 &phw->control_cache[0]
667 struct hpi_hw_obj *phw = (struct hpi_hw_obj *)pao->priv;
704 iowrite32(dw2040_reset, phw->dw2040_HPICSR + HPI_RESET);
711 delay = ioread32(phw->dw2040_HPICSR + HPI_RESET);
719 iowrite32(0x00000003, phw->dw2040_HPICSR + HPI_DATA_WIDTH);
723 iowrite32(0x60000000, phw->dw2040_HPICSR + INTERRUPT_MASK_SET);
729 iowrite32(dw2040_reset, phw->dw2040_HPICSR + HPI_RESET);
731 phw->ado[0].c_dsp_rev = 'B'; /* revB */
732 phw->ado[1].c_dsp_rev = 'B'; /* revB */
736 iowrite32(dw2040_reset, phw->dw2040_HPICSR + HPI_RESET);
738 iowrite32(dw2040_reset, phw->dw2040_HPICSR + HPI_RESET);
742 iowrite32(dw2040_reset, phw->dw2040_HPICSR + HPI_RESET);
745 delay = ioread32(phw->dw2040_HPICSR + HPI_RESET);
748 for (dsp_index = 0; dsp_index < phw->num_dsp; dsp_index++) {
749 struct dsp_obj *pdo = &phw->ado[dsp_index];
785 delay = ioread32(phw->dw2040_HPICSR +
797 delay = ioread32(phw->dw2040_HPICSR +
803 delay = ioread32(phw->dw2040_HPICSR +
930 delay = ioread32(phw->dw2040_HPICSR + HPI_RESET);
1075 delay = ioread32(phw->dw2040_HPICSR + HPI_RESET);
1115 phw->num_dsp = 2;
1326 struct hpi_hw_obj *phw = (struct hpi_hw_obj *)pao->priv;
1327 struct dsp_obj *pdo = &phw->ado[dsp_index];
1336 if (dsp_index >= phw->num_dsp)
1349 if (phw->message_buffer_address_on_dsp == 0) {
1355 phw->message_buffer_address_on_dsp = address;
1361 address = phw->message_buffer_address_on_dsp;
1381 if (phw->response_buffer_address_on_dsp == 0) {
1389 phw->response_buffer_address_on_dsp = address;
1394 address = phw->response_buffer_address_on_dsp;
1612 struct hpi_hw_obj *phw = (struct hpi_hw_obj *)pao->priv;
1615 hPI_error = ioread32(phw->dw2040_HPICSR + HPI_ERROR_REPORT);
1618 iowrite32(0L, phw->dw2040_HPICSR + HPI_ERROR_REPORT);
1619 phw->pCI2040HPI_error_count++;
1675 struct hpi_hw_obj *phw = (struct hpi_hw_obj *)pao->priv;
1676 struct dsp_obj *pdo = &phw->ado[dsp_index];
1723 (u32 *)&phw->control_cache[0],