Lines Matching refs:SS_CSR
165 #define SS_CSR(t) (SER_BASE+t)
563 __raw_writeq(M_SYNCSER_CMD_RX_RESET | M_SYNCSER_CMD_TX_RESET, SS_CSR(R_SER_CMD));
565 __raw_writeq(M_SYNCSER_MSB_FIRST, SS_CSR(R_SER_MODE));
566 __raw_writeq(32, SS_CSR(R_SER_MINFRM_SZ));
567 __raw_writeq(32, SS_CSR(R_SER_MAXFRM_SZ));
569 __raw_writeq(1, SS_CSR(R_SER_TX_RD_THRSH));
570 __raw_writeq(4, SS_CSR(R_SER_TX_WR_THRSH));
571 __raw_writeq(8, SS_CSR(R_SER_RX_RD_THRSH));
576 SS_CSR(R_SER_LINE_MODE));
664 if (__raw_readq(SS_CSR(R_SER_DMA_DSCR_COUNT_RX))||
665 __raw_readq(SS_CSR(R_SER_DMA_DSCR_COUNT_TX))) {
682 SS_CSR(R_SER_DMA_CONFIG0_RX));
683 __raw_writeq(M_DMA_L2CA, SS_CSR(R_SER_DMA_CONFIG1_RX));
684 __raw_writeq(s->dma_adc.descrtab_phys, SS_CSR(R_SER_DMA_DSCR_BASE_RX));
686 __raw_writeq(V_DMA_RINGSZ(DMA_DESCR), SS_CSR(R_SER_DMA_CONFIG0_TX));
687 __raw_writeq(M_DMA_L2CA | M_DMA_NO_DSCR_UPDT, SS_CSR(R_SER_DMA_CONFIG1_TX));
688 __raw_writeq(s->dma_dac.descrtab_phys, SS_CSR(R_SER_DMA_DSCR_BASE_TX));
691 __raw_writeq(DMA_DESCR, SS_CSR(R_SER_DMA_DSCR_COUNT_RX));
693 __raw_writeq(M_SYNCSER_DMA_RX_EN | M_SYNCSER_DMA_TX_EN, SS_CSR(R_SER_DMA_ENABLE));
696 SS_CSR(R_SER_INT_MASK));
701 __raw_writeq(M_SYNCSER_CMD_TX_EN, SS_CSR(R_SER_CMD));
703 __raw_writeq(M_SYNCSER_CMD_RX_EN | M_SYNCSER_CMD_TX_EN, SS_CSR(R_SER_CMD));
706 while ((__raw_readq(SS_CSR(R_SER_STATUS)) & 0xf1) != 1)
711 (unsigned int)(__raw_readq(SS_CSR(R_SER_STATUS)) & 0xffffffff)));
752 __raw_writeq(1, SS_CSR(R_SER_DMA_DSCR_COUNT_TX));
918 status = intflag ? __raw_readq(SS_CSR(R_SER_STATUS)) : 0;
922 hwptr = (unsigned) (((__raw_readq(SS_CSR(R_SER_DMA_CUR_DSCR_ADDR_RX)) & M_DMA_CURDSCR_ADDR) -
984 __raw_writeq(diff, SS_CSR(R_SER_DMA_DSCR_COUNT_RX));
1040 __raw_writeq(1, SS_CSR(R_SER_DMA_DSCR_COUNT_RX));
1065 hwptr = (unsigned) (((__raw_readq(SS_CSR(R_SER_DMA_CUR_DSCR_ADDR_TX)) & M_DMA_CURDSCR_ADDR) -
1612 while ((count = __raw_readq(SS_CSR(R_SER_DMA_DSCR_COUNT_TX))) ||
1625 hwptr = (int)(((__raw_readq(SS_CSR(R_SER_DMA_CUR_DSCR_ADDR_TX)) & M_DMA_CURDSCR_ADDR) -
1798 hwptr = (unsigned) (((__raw_readq(SS_CSR(R_SER_DMA_CUR_DSCR_ADDR_TX)) & M_DMA_CURDSCR_ADDR) -
1861 __raw_writeq(cnt/FRAME_SAMPLE_BYTES, SS_CSR(R_SER_DMA_DSCR_COUNT_TX));
1998 (int)(((__raw_readq(SS_CSR(R_SER_DMA_CUR_DSCR_ADDR_TX)) & M_DMA_CURDSCR_ADDR) -
2007 (int)(((__raw_readq(SS_CSR(R_SER_DMA_CUR_DSCR_ADDR_RX)) & M_DMA_CURDSCR_ADDR) -
2391 "cs4297a: status = %08x\n", (int)__raw_readq(SS_CSR(R_SER_STATUS_DEBUG))));
2417 if (__raw_readq(SS_CSR(R_SER_DMA_DSCR_COUNT_TX)) != 0) {
2419 while (__raw_readq(SS_CSR(R_SER_DMA_DSCR_COUNT_TX)))
2529 status = __raw_readq(SS_CSR(R_SER_STATUS_DEBUG));
2536 status = __raw_readq(SS_CSR(R_SER_STATUS));
2548 while (__raw_readq(SS_CSR(R_SER_DMA_DSCR_COUNT_RX)))
2550 newptr = (unsigned) (((__raw_readq(SS_CSR(R_SER_DMA_CUR_DSCR_ADDR_RX)) & M_DMA_CURDSCR_ADDR) -
2558 __raw_writeq(DMA_DESCR, SS_CSR(R_SER_DMA_DSCR_COUNT_RX));