Lines Matching refs:OPTi9XX_MC_REG
104 #define OPTi9XX_MC_REG(n) n
1027 snd_miro_write_mask(chip, OPTi9XX_MC_REG(1), 0x80, 0x80);
1028 snd_miro_write_mask(chip, OPTi9XX_MC_REG(2), 0x20, 0x20); /* OPL4 */
1029 snd_miro_write_mask(chip, OPTi9XX_MC_REG(5), 0x02, 0x02);
1033 snd_miro_write_mask(chip, OPTi9XX_MC_REG(6), 0x02, 0x02);
1034 snd_miro_write_mask(chip, OPTi9XX_MC_REG(3), 0xf0, 0xff);
1038 snd_miro_write_mask(chip, OPTi9XX_MC_REG(4), 0x00, 0x0c);
1067 snd_miro_write_mask(chip, OPTi9XX_MC_REG(1), wss_base_bits << 4, 0x30);
1168 snd_miro_write_mask(chip, OPTi9XX_MC_REG(6),
1187 value = snd_miro_read(chip, OPTi9XX_MC_REG(1));
1188 if (value != 0xff && value != inb(chip->mc_base + OPTi9XX_MC_REG(1)))
1189 if (value == snd_miro_read(chip, OPTi9XX_MC_REG(1)))