Lines Matching defs:port
101 * Configure the upstream port, and configure the upstream
102 * port as the port to which ingress and egress monitor frames
115 * 01:80:c2:00:00:2x to the CPU port.
121 * 01:80:c2:00:00:0x to the CPU port.
168 * Initialise cross-chip port VLAN table to reset defaults.
191 * ports, but force the CPU port and all DSA ports to 1000 Mb/s
200 * Do not limit the period of time that this port can be
202 * this port can pause the remote end.
218 * If this is the upstream port for this switch, enable
236 * CPU port, enable learn messages to be sent to this port.
241 * Port based VLAN map: give each port its own address
242 * database, allow the CPU port to talk to each of the 'real'
244 * the upstream port.
263 * on this port, do a destination address lookup on all
265 * send a copy of all transmitted/received frames on this port
283 * a port bitmap that has only the bit for this port set and
290 * database entries that this port is allowed to use.
347 static int mv88e6123_61_65_port_to_phy_addr(int port)
349 if (port >= 0 && port <= 4)
350 return port;
355 mv88e6123_61_65_phy_read(struct dsa_switch *ds, int port, int regnum)
357 int addr = mv88e6123_61_65_port_to_phy_addr(port);
363 int port, int regnum, u16 val)
365 int addr = mv88e6123_61_65_port_to_phy_addr(port);
403 mv88e6123_61_65_get_strings(struct dsa_switch *ds, int port, uint8_t *data)
406 mv88e6123_61_65_hw_stats, port, data);
411 int port, uint64_t *data)
414 mv88e6123_61_65_hw_stats, port, data);