Lines Matching refs:viafb_write_reg_mask
412 viafb_write_reg_mask(CR79, VIACR, 0x07, BIT0 + BIT1 + BIT2);
442 viafb_write_reg_mask(CRA2, VIACR, 0xC0, BIT7 + BIT6);
454 viafb_write_reg_mask(CRA2, VIACR, 0x00, BIT7);
485 viafb_write_reg_mask(CRA2, VIACR, 0x08, BIT3);
497 viafb_write_reg_mask(CRA2, VIACR, 0x00, BIT3);
587 viafb_write_reg_mask(CR99, VIACR, 0x08,
640 viafb_write_reg_mask(CR79, VIACR, 0x00,
666 viafb_write_reg_mask(CR6A, VIACR, 0x01, BIT0);
688 viafb_write_reg_mask(CRD4, VIACR, 0, BIT1);
691 viafb_write_reg_mask(CRD3, VIACR, 0xC0, BIT6 + BIT7);
697 viafb_write_reg_mask(CR6A, VIACR, 0, BIT3);
700 viafb_write_reg_mask(CR91, VIACR, 0xC0, BIT6 + BIT7);
704 viafb_write_reg_mask(SR2A, VIASR, 0, BIT0 + BIT1 + BIT2 + BIT3);
710 viafb_write_reg_mask(CRD2, VIACR, 0x80, BIT7);
716 viafb_write_reg_mask(CRD2, VIACR, 0x40, BIT6);
722 viafb_write_reg_mask(CRD2, VIACR, 0xC0, BIT6 + BIT7);
735 viafb_write_reg_mask(CRD2, VIACR, 0x00, BIT0 + BIT1);
737 viafb_write_reg_mask(CRD2, VIACR, 0x03, BIT0 + BIT1);
744 viafb_write_reg_mask(CR91, VIACR, 0, BIT0);
746 viafb_write_reg_mask(CR91, VIACR, 0, BIT6 + BIT7);
748 viafb_write_reg_mask(CR6A, VIACR, 0x08, BIT3);
753 viafb_write_reg_mask(CRD3, VIACR, 0, BIT0);
755 viafb_write_reg_mask(CRD3, VIACR, 0, BIT6 + BIT7);
757 viafb_write_reg_mask(CRD4, VIACR, 0x02, BIT1);
762 viafb_write_reg_mask(SR2A, VIASR, 0x0F, BIT0 + BIT1 + BIT2 + BIT3);
768 viafb_write_reg_mask(CRD2, VIACR, 0, BIT7);
774 viafb_write_reg_mask(CRD2, VIACR, 0, BIT6);
780 viafb_write_reg_mask(CRD2, VIACR, 0, BIT6 + BIT7);
792 viafb_write_reg_mask(SR1E, VIASR, 0x00, 0x30);
813 viafb_write_reg_mask(SR2A, VIASR, 0x00, 0x0F);
815 viafb_write_reg_mask(SR3D, VIASR, 0x00, 0x20);
817 viafb_write_reg_mask(CR91, VIACR, 0x80, 0x80);
819 viafb_write_reg_mask(CR6B, VIACR, 0x00, 0x08);
823 viafb_write_reg_mask(CR79, VIACR, 0x00, 0x01);
825 viafb_write_reg_mask(SR16, VIASR, 0x00, 0x40);
827 viafb_write_reg_mask(CR6B, VIACR, 0x00, 0x08);
829 viafb_write_reg_mask(CR6A, VIACR, 0x00, 0x80);
837 viafb_write_reg_mask(SR1E, VIASR, 0x30, 0x30);
859 viafb_write_reg_mask(SR2A, VIASR, 0x0F, 0x0F);
861 viafb_write_reg_mask(SR3D, VIASR, 0x20, 0x20);
863 viafb_write_reg_mask(CR91, VIACR, 0x00, 0x80);
868 viafb_write_reg_mask(CR97, VIACR, 0x00, 0x10);
870 viafb_write_reg_mask(CR99, VIACR, 0x00, 0x10);
873 viafb_write_reg_mask(CR97, VIACR, 0x10, 0x10);
875 viafb_write_reg_mask(CR99, VIACR, 0x10, 0x10);
878 viafb_write_reg_mask(CR6A, VIACR, 0x48, 0x48);
883 viafb_write_reg_mask(SR16, VIASR, 0x40, 0x40);
885 viafb_write_reg_mask(CR6A, VIACR, 0x00, 0x80);
888 viafb_write_reg_mask(CR6A, VIACR, 0x80, 0x80);
898 viafb_write_reg_mask(CR91, VIACR, 0x11, 0x11);
903 viafb_write_reg_mask(CR91, VIACR, (u8) data, (u8) mask);
908 viafb_write_reg_mask(CR6A, VIACR, 0x00, 0x08);
916 viafb_write_reg_mask(CR91, VIACR, 0x11, 0x11);
919 viafb_write_reg_mask(CR6A, VIACR, 0x08, 0x08);
924 viafb_write_reg_mask(CR91, VIACR, (u8) data, (u8) mask);
940 viafb_write_reg_mask(CR88, VIACR, (bdithering | bdual), BIT4 + BIT0);