Lines Matching refs:VML_WRITE32
709 VML_WRITE32(par, VML_RCOMPSTAT, 0);
713 VML_WRITE32(par, VML_DSPCCNTR,
720 VML_WRITE32(par, VML_PIPEACONF, 0);
837 VML_WRITE32(par, VML_HTOTAL_A, ((htotal - 1) << 16) | (hactive - 1));
838 VML_WRITE32(par, VML_HBLANK_A,
840 VML_WRITE32(par, VML_HSYNC_A,
842 VML_WRITE32(par, VML_VTOTAL_A, ((vtotal - 1) << 16) | (vactive - 1));
843 VML_WRITE32(par, VML_VBLANK_A,
845 VML_WRITE32(par, VML_VSYNC_A,
847 VML_WRITE32(par, VML_DSPCSTRIDE, vinfo->stride);
848 VML_WRITE32(par, VML_DSPCSIZE,
850 VML_WRITE32(par, VML_DSPCPOS, 0x00000000);
851 VML_WRITE32(par, VML_DSPARB, VML_FIFO_DEFAULT);
852 VML_WRITE32(par, VML_BCLRPAT_A, 0x00000000);
853 VML_WRITE32(par, VML_CANVSCLR_A, 0x00000000);
854 VML_WRITE32(par, VML_PIPEASRC,
858 VML_WRITE32(par, VML_PIPEACONF, VML_PIPE_ENABLE);
860 VML_WRITE32(par, VML_DSPCCNTR, dspcntr);
862 VML_WRITE32(par, VML_DSPCADDR, (u32) vinfo->vram_start +
866 VML_WRITE32(par, VML_RCOMPSTAT, VML_MDVO_PAD_ENABLE);
903 VML_WRITE32(par, VML_PIPEACONF, cur & ~VML_PIPE_FORCE_BORDER);
910 VML_WRITE32(par, VML_PIPEACONF, cur | VML_PIPE_FORCE_BORDER);
950 VML_WRITE32(par, VML_DSPCADDR, (u32) vinfo->vram_start +