Lines Matching refs:savage_out32
319 savage_out32(0x48C18, savage_in32(0x48C18, par) & 0x3FF0, par);
321 savage_out32(0x48C14,
325 savage_out32(0x48C10, 0x78207220, par);
326 savage_out32(0x48C0C, 0, par);
328 savage_out32(0x48C18, savage_in32(0x48C18, par) | 0x0C, par);
334 savage_out32(0x48C18, savage_in32(0x48C18, par) & 0x3FF0, par);
336 savage_out32(0x48C10, 0x00700040, par);
337 savage_out32(0x48C0C, 0, par);
339 savage_out32(0x48C18, savage_in32(0x48C18, par) | 0x08, par);
343 savage_out32(0x48C18, 0, par);
345 savage_out32(0x48C18,
349 savage_out32(0x48A30, 0, par);
351 savage_out32(0x48C18, savage_in32(0x48C18, par) | 0x00280000,
369 savage_out32(MONO_PAT_0, ~0, par);
370 savage_out32(MONO_PAT_1, ~0, par);
373 savage_out32(0x8128, ~0, par); /* enable all write planes */
374 savage_out32(0x812C, ~0, par); /* enable all read planes */
836 savage_out32(FIFO_CONTROL_REG, reg->MMPR0, par);
837 savage_out32(MIU_CONTROL_REG, reg->MMPR1, par);
838 savage_out32(STREAMS_TIMEOUT_REG, reg->MMPR2, par);
839 savage_out32(MISC_TIMEOUT_REG, reg->MMPR3, par);
1460 savage_out32(FIFO_CONTROL_REG, reg->MMPR0, par);
1462 savage_out32(MIU_CONTROL_REG, reg->MMPR1, par);
1464 savage_out32(STREAMS_TIMEOUT_REG, reg->MMPR2, par);
1466 savage_out32(MISC_TIMEOUT_REG, reg->MMPR3, par);