Lines Matching refs:fbi
54 static int is_s3c2412(struct s3c2410fb_info *fbi)
56 return (fbi->drv_type == DRV_S3C2412);
66 struct s3c2410fb_info *fbi = info->par;
67 void __iomem *regs = fbi->io;
90 static unsigned int s3c2410fb_calc_pixclk(struct s3c2410fb_info *fbi,
93 unsigned long clk = fbi->clk_rate;
118 struct s3c2410fb_info *fbi = info->par;
119 struct s3c2410fb_mach_info *mach_info = fbi->dev->platform_data;
165 fbi->regs.lcdcon5 = display->lcdcon5;
167 fbi->regs.lcdcon1 = display->type;
247 const struct s3c2410fb_info *fbi = info->par;
278 dev_err(fbi->dev, "invalid bpp %d\n",
307 const struct s3c2410fb_info *fbi = info->par;
339 dev_err(fbi->dev, "invalid bpp %d\n",
368 struct s3c2410fb_info *fbi = info->par;
369 void __iomem *regs = fbi->io;
370 int type = fbi->regs.lcdcon1 & S3C2410_LCDCON1_TFT;
374 clkdiv = DIV_ROUND_UP(s3c2410fb_calc_pixclk(fbi, var->pixclock), 2);
381 s3c2410fb_calculate_tft_lcd_regs(info, &fbi->regs);
386 s3c2410fb_calculate_stn_lcd_regs(info, &fbi->regs);
391 fbi->regs.lcdcon1 |= S3C2410_LCDCON1_CLKVAL(clkdiv);
396 dprintk("lcdcon[1] = 0x%08lx\n", fbi->regs.lcdcon1);
397 dprintk("lcdcon[2] = 0x%08lx\n", fbi->regs.lcdcon2);
398 dprintk("lcdcon[3] = 0x%08lx\n", fbi->regs.lcdcon3);
399 dprintk("lcdcon[4] = 0x%08lx\n", fbi->regs.lcdcon4);
400 dprintk("lcdcon[5] = 0x%08lx\n", fbi->regs.lcdcon5);
402 writel(fbi->regs.lcdcon1 & ~S3C2410_LCDCON1_ENVID,
404 writel(fbi->regs.lcdcon2, regs + S3C2410_LCDCON2);
405 writel(fbi->regs.lcdcon3, regs + S3C2410_LCDCON3);
406 writel(fbi->regs.lcdcon4, regs + S3C2410_LCDCON4);
407 writel(fbi->regs.lcdcon5, regs + S3C2410_LCDCON5);
412 fbi->regs.lcdcon1 |= S3C2410_LCDCON1_ENVID,
413 writel(fbi->regs.lcdcon1, regs + S3C2410_LCDCON1);
447 static void schedule_palette_update(struct s3c2410fb_info *fbi,
452 void __iomem *irq_base = fbi->irq_base;
456 fbi->palette_buffer[regno] = val;
458 if (!fbi->palette_ready) {
459 fbi->palette_ready = 1;
483 struct s3c2410fb_info *fbi = info->par;
484 void __iomem *regs = fbi->io;
514 schedule_palette_update(fbi, regno, val);
530 static void s3c2410fb_lcd_enable(struct s3c2410fb_info *fbi, int enable)
537 fbi->regs.lcdcon1 |= S3C2410_LCDCON1_ENVID;
539 fbi->regs.lcdcon1 &= ~S3C2410_LCDCON1_ENVID;
541 writel(fbi->regs.lcdcon1, fbi->io + S3C2410_LCDCON1);
562 struct s3c2410fb_info *fbi = info->par;
563 void __iomem *tpal_reg = fbi->io;
567 tpal_reg += is_s3c2412(fbi) ? S3C2412_TPAL : S3C2410_TPAL;
570 s3c2410fb_lcd_enable(fbi, 0);
572 s3c2410fb_lcd_enable(fbi, 1);
636 struct s3c2410fb_info *fbi = info->par;
640 dprintk("map_video_memory(fbi=%p) map_size %u\n", fbi, map_size);
642 info->screen_base = dma_alloc_writecombine(fbi->dev, map_size,
662 struct s3c2410fb_info *fbi = info->par;
664 dma_free_writecombine(fbi->dev, PAGE_ALIGN(info->fix.smem_len),
682 struct s3c2410fb_info *fbi = info->par;
683 struct s3c2410fb_mach_info *mach_info = fbi->dev->platform_data;
685 void __iomem *regs = fbi->io;
689 if (is_s3c2412(fbi)) {
721 static void s3c2410fb_write_palette(struct s3c2410fb_info *fbi)
724 void __iomem *regs = fbi->io;
726 fbi->palette_ready = 0;
729 unsigned long ent = fbi->palette_buffer[i];
741 fbi->palette_buffer[i] = PALETTE_BUFF_CLEAR;
743 fbi->palette_ready = 1; /* retry */
749 struct s3c2410fb_info *fbi = dev_id;
750 void __iomem *irq_base = fbi->irq_base;
754 if (fbi->palette_ready)
755 s3c2410fb_write_palette(fbi);