Lines Matching refs:sim_data
619 nv3_sim_state sim_data;
625 sim_data.pix_bpp = (char)pixelDepth;
626 sim_data.enable_video = 0;
627 sim_data.enable_mp = 0;
628 sim_data.video_scale = 1;
629 sim_data.memory_width = (NV_RD32(&chip->PEXTDEV[0x00000000/4], 0) & 0x10) ?
631 sim_data.memory_width = 128;
633 sim_data.mem_latency = 9;
634 sim_data.mem_aligned = 1;
635 sim_data.mem_page_miss = 11;
636 sim_data.gr_during_vid = 0;
637 sim_data.pclk_khz = VClk;
638 sim_data.mclk_khz = MClk;
639 nv3CalcArbitration(&fifo_data, &sim_data);
808 nv4_sim_state sim_data;
818 sim_data.pix_bpp = (char)pixelDepth;
819 sim_data.enable_video = 0;
820 sim_data.enable_mp = 0;
821 sim_data.memory_width = (NV_RD32(&chip->PEXTDEV[0x00000000/4], 0) & 0x10) ?
823 sim_data.mem_latency = (char)cfg1 & 0x0F;
824 sim_data.mem_aligned = 1;
825 sim_data.mem_page_miss = (char)(((cfg1 >> 4) &0x0F) + ((cfg1 >> 31) & 0x01));
826 sim_data.gr_during_vid = 0;
827 sim_data.pclk_khz = VClk;
828 sim_data.mclk_khz = MClk;
829 sim_data.nvclk_khz = NVClk;
830 nv4CalcArbitration(&fifo_data, &sim_data);
1071 nv10_sim_state sim_data;
1081 sim_data.pix_bpp = (char)pixelDepth;
1082 sim_data.enable_video = 0;
1083 sim_data.enable_mp = 0;
1084 sim_data.memory_type = (NV_RD32(&chip->PFB[0x00000200/4], 0) & 0x01) ?
1086 sim_data.memory_width = (NV_RD32(&chip->PEXTDEV[0x00000000/4], 0) & 0x10) ?
1088 sim_data.mem_latency = (char)cfg1 & 0x0F;
1089 sim_data.mem_aligned = 1;
1090 sim_data.mem_page_miss = (char)(((cfg1 >> 4) &0x0F) + ((cfg1 >> 31) & 0x01));
1091 sim_data.gr_during_vid = 0;
1092 sim_data.pclk_khz = VClk;
1093 sim_data.mclk_khz = MClk;
1094 sim_data.nvclk_khz = NVClk;
1095 nv10CalcArbitration(&fifo_data, &sim_data);
1116 nv10_sim_state sim_data;
1132 sim_data.pix_bpp = (char)pixelDepth;
1133 sim_data.enable_video = 0;
1134 sim_data.enable_mp = 0;
1137 pci_read_config_dword(dev, 0x7C, &sim_data.memory_type);
1139 sim_data.memory_type = (sim_data.memory_type >> 12) & 1;
1141 sim_data.memory_width = 64;
1142 sim_data.mem_latency = 3;
1143 sim_data.mem_aligned = 1;
1144 sim_data.mem_page_miss = 10;
1145 sim_data.gr_during_vid = 0;
1146 sim_data.pclk_khz = VClk;
1147 sim_data.mclk_khz = MClk;
1148 sim_data.nvclk_khz = NVClk;
1149 nv10CalcArbitration(&fifo_data, &sim_data);