Lines Matching refs:memory_width
193 int memory_width;
214 int memory_width;
235 int memory_width;
273 ns = 1000000 * ainfo->vburst_size/(state->memory_width/8)/state->mclk_khz;
285 ns = 1000000 * (ainfo->gburst_size/(state->memory_width/8))/state->mclk_khz;
344 ns = 1000000*(misses*state->mem_page_miss + ainfo->vburst_size)/(state->memory_width/8)/state->mclk_khz;
360 ns = 1000000*(misses*state->mem_page_miss + ainfo->gburst_size/(state->memory_width/8))/state->mclk_khz;
370 ns = 1000000*(misses*state->mem_page_miss + mburst_size/(state->memory_width/8))/state->mclk_khz;
381 ns = 1000000*ainfo->gburst_size/(state->memory_width/8)/state->mclk_khz;
388 ns = 1000000*ainfo->vburst_size/(state->memory_width/8)/state->mclk_khz;
439 eburst_size = state->memory_width * 1;
452 ens = 1000000*(state->mem_page_miss + eburst_size/(state->memory_width/8) +refresh_cycle)/state->mclk_khz;
464 mns = 1000000 * (mmisses*state->mem_page_miss + mburst_size/(state->memory_width/8) + refresh_cycle)/state->mclk_khz;
479 gns = 1000000*(gmisses*state->mem_page_miss + ainfo->gburst_size/(state->memory_width/8) + refresh_cycle)/state->mclk_khz;
491 vns = 1000000*(vmisses*state->mem_page_miss + ainfo->vburst_size/(state->memory_width/8) + refresh_cycle)/state->mclk_khz;
629 sim_data.memory_width = (NV_RD32(&chip->PEXTDEV[0x00000000/4], 0) & 0x10) ?
631 sim_data.memory_width = 128;
674 width = arb->memory_width >> 6;
821 sim_data.memory_width = (NV_RD32(&chip->PEXTDEV[0x00000000/4], 0) & 0x10) ?
865 width = arb->memory_width/64;
893 if (arb->memory_width == 64) /* 64 bit bus */
898 if (arb->memory_width == 64) /* 64 bit bus */
903 if ((!video_enable) && (arb->memory_width == 128))
1086 sim_data.memory_width = (NV_RD32(&chip->PEXTDEV[0x00000000/4], 0) & 0x10) ?
1141 sim_data.memory_width = 64;