Lines Matching refs:fbi
165 static void set_mode(struct pxa168fb_info *fbi, struct fb_var_screeninfo *var,
168 struct fb_info *info = fbi->info;
197 struct pxa168fb_info *fbi = info->par;
207 fbi->pix_fmt = pix_fmt;
243 static void set_clock_divider(struct pxa168fb_info *fbi,
261 dev_err(fbi->dev, "Input refresh or pixclock is wrong.\n");
277 divider_int = clk_get_rate(fbi->clk) / needed_pixclk;
281 dev_warn(fbi->dev, "Warning: clock source is too slow."
290 writel(x, fbi->reg_base + LCD_CFG_SCLK_DIV);
293 static void set_dma_control0(struct pxa168fb_info *fbi)
300 x = readl(fbi->reg_base + LCD_SPU_DMA_CTRL0);
302 x |= fbi->active ? CFG_GRA_ENA(1) : CFG_GRA_ENA(0);
308 if (fbi->pix_fmt == PIX_FMT_PSEUDOCOLOR)
315 x |= (fbi->pix_fmt >> 1) << 16;
323 x |= ((fbi->pix_fmt & 1) ^ (fbi->panel_rbswap)) << 12;
325 writel(x, fbi->reg_base + LCD_SPU_DMA_CTRL0);
328 static void set_dma_control1(struct pxa168fb_info *fbi, int sync)
337 x = readl(fbi->reg_base + LCD_SPU_DMA_CTRL1);
347 writel(x, fbi->reg_base + LCD_SPU_DMA_CTRL1);
352 struct pxa168fb_info *fbi = info->par;
359 addr = fbi->fb_start_dma + (pixel_offset * (var->bits_per_pixel >> 3));
360 writel(addr, fbi->reg_base + LCD_CFG_GRA_START_ADDR0);
365 struct pxa168fb_info *fbi = info->par;
366 struct pxa168fb_mach_info *mi = fbi->dev->platform_data;
372 x = readl(fbi->reg_base + LCD_SPU_DUMB_CTRL) & 0x00000001;
374 x |= (fbi->is_blanked ? 0x7 : mi->dumb_mode) << 28;
385 writel(x, fbi->reg_base + LCD_SPU_DUMB_CTRL);
390 struct pxa168fb_info *fbi = info->par;
398 writel((y << 16) | x, fbi->reg_base + LCD_SPUT_V_H_TOTAL);
403 struct pxa168fb_info *fbi = info->par;
409 mi = fbi->dev->platform_data;
414 if (fbi->pix_fmt == PIX_FMT_PSEUDOCOLOR)
424 x = readl(fbi->reg_base + LCD_SPU_DUMB_CTRL);
425 writel(x & ~1, fbi->reg_base + LCD_SPU_DUMB_CTRL);
431 fbi->reg_base + LCD_SPU_V_H_ACTIVE);
439 set_clock_divider(fbi, &mode);
442 set_dma_control0(fbi);
443 set_dma_control1(fbi, info->var.sync);
448 x = readl(fbi->reg_base + LCD_CFG_GRA_PITCH);
450 writel(x, fbi->reg_base + LCD_CFG_GRA_PITCH);
452 fbi->reg_base + LCD_SPU_GRA_HPXL_VLN);
454 fbi->reg_base + LCD_SPU_GZM_HPXL_VLN);
463 fbi->reg_base + LCD_SPU_H_PORCH);
465 fbi->reg_base + LCD_SPU_V_PORCH);
470 x = readl(fbi->reg_base + LCD_SPU_DUMB_CTRL);
471 writel(x | 1, fbi->reg_base + LCD_SPU_DUMB_CTRL);
494 struct pxa168fb_info *fbi = info->par;
505 fbi->pseudo_palette[regno] = val;
510 writel(val, fbi->reg_base + LCD_SPU_SRAM_WRDAT);
511 writel(0x8300 | regno, fbi->reg_base + LCD_SPU_SRAM_CTRL);
519 struct pxa168fb_info *fbi = info->par;
521 fbi->is_blanked = (blank == FB_BLANK_UNBLANK) ? 0 : 1;
537 struct pxa168fb_info *fbi = dev_id;
538 u32 isr = readl(fbi->reg_base + SPU_IRQ_ISR);
543 fbi->reg_base + SPU_IRQ_ISR);
565 struct pxa168fb_info *fbi = info->par;
586 dev_dbg(fbi->dev, "pxa168fb: find best mode: res = %dx%d\n",
606 struct pxa168fb_info *fbi = 0;
642 fbi = info->par;
643 fbi->info = info;
644 fbi->clk = clk;
645 fbi->dev = info->dev = &pdev->dev;
646 fbi->panel_rbswap = mi->panel_rbswap;
647 fbi->is_blanked = 0;
648 fbi->active = mi->active;
666 info->pseudo_palette = fbi->pseudo_palette;
671 fbi->reg_base = ioremap_nocache(res->start, resource_size(res));
672 if (fbi->reg_base == NULL) {
682 info->screen_base = dma_alloc_writecombine(fbi->dev, info->fix.smem_len,
683 &fbi->fb_start_dma, GFP_KERNEL);
689 info->fix.smem_start = (unsigned long)fbi->fb_start_dma;
695 set_mode(fbi, &info->var, mi->modes, mi->pix_fmt, 1);
718 clk_enable(fbi->clk);
725 writel(0, fbi->reg_base + LCD_SPU_BLANKCOLOR);
726 writel(mi->io_pin_allocation_mode, fbi->reg_base + SPU_IOPAD_CONTROL);
727 writel(0, fbi->reg_base + LCD_CFG_GRA_START_ADDR1);
728 writel(0, fbi->reg_base + LCD_SPU_GRA_OVSA_HPXL_VLN);
729 writel(0, fbi->reg_base + LCD_SPU_SRAM_PARA0);
731 fbi->reg_base + LCD_SPU_SRAM_PARA1);
745 info->fix.id, fbi);
755 writel(GRA_FRAME_IRQ0_ENA(0x1), fbi->reg_base + SPU_IRQ_ENA);
767 platform_set_drvdata(pdev, fbi);
771 free_irq(irq, fbi);
775 clk_disable(fbi->clk);
777 dma_free_coherent(fbi->dev, info->fix.smem_len,
778 info->screen_base, fbi->fb_start_dma);