Lines Matching refs:MX3FB_REG_OFFSET
39 #define MX3FB_REG_OFFSET 0xB4
42 #define SDC_COM_CONF (0xB4 - MX3FB_REG_OFFSET)
43 #define SDC_GW_CTRL (0xB8 - MX3FB_REG_OFFSET)
44 #define SDC_FG_POS (0xBC - MX3FB_REG_OFFSET)
45 #define SDC_BG_POS (0xC0 - MX3FB_REG_OFFSET)
46 #define SDC_CUR_POS (0xC4 - MX3FB_REG_OFFSET)
47 #define SDC_PWM_CTRL (0xC8 - MX3FB_REG_OFFSET)
48 #define SDC_CUR_MAP (0xCC - MX3FB_REG_OFFSET)
49 #define SDC_HOR_CONF (0xD0 - MX3FB_REG_OFFSET)
50 #define SDC_VER_CONF (0xD4 - MX3FB_REG_OFFSET)
51 #define SDC_SHARP_CONF_1 (0xD8 - MX3FB_REG_OFFSET)
52 #define SDC_SHARP_CONF_2 (0xDC - MX3FB_REG_OFFSET)
66 #define DI_DISP_IF_CONF (0x0124 - MX3FB_REG_OFFSET)
67 #define DI_DISP_SIG_POL (0x0128 - MX3FB_REG_OFFSET)
68 #define DI_SER_DISP1_CONF (0x012C - MX3FB_REG_OFFSET)
69 #define DI_SER_DISP2_CONF (0x0130 - MX3FB_REG_OFFSET)
70 #define DI_HSP_CLK_PER (0x0134 - MX3FB_REG_OFFSET)
71 #define DI_DISP0_TIME_CONF_1 (0x0138 - MX3FB_REG_OFFSET)
72 #define DI_DISP0_TIME_CONF_2 (0x013C - MX3FB_REG_OFFSET)
73 #define DI_DISP0_TIME_CONF_3 (0x0140 - MX3FB_REG_OFFSET)
74 #define DI_DISP1_TIME_CONF_1 (0x0144 - MX3FB_REG_OFFSET)
75 #define DI_DISP1_TIME_CONF_2 (0x0148 - MX3FB_REG_OFFSET)
76 #define DI_DISP1_TIME_CONF_3 (0x014C - MX3FB_REG_OFFSET)
77 #define DI_DISP2_TIME_CONF_1 (0x0150 - MX3FB_REG_OFFSET)
78 #define DI_DISP2_TIME_CONF_2 (0x0154 - MX3FB_REG_OFFSET)
79 #define DI_DISP2_TIME_CONF_3 (0x0158 - MX3FB_REG_OFFSET)
80 #define DI_DISP3_TIME_CONF (0x015C - MX3FB_REG_OFFSET)
81 #define DI_DISP0_DB0_MAP (0x0160 - MX3FB_REG_OFFSET)
82 #define DI_DISP0_DB1_MAP (0x0164 - MX3FB_REG_OFFSET)
83 #define DI_DISP0_DB2_MAP (0x0168 - MX3FB_REG_OFFSET)
84 #define DI_DISP0_CB0_MAP (0x016C - MX3FB_REG_OFFSET)
85 #define DI_DISP0_CB1_MAP (0x0170 - MX3FB_REG_OFFSET)
86 #define DI_DISP0_CB2_MAP (0x0174 - MX3FB_REG_OFFSET)
87 #define DI_DISP1_DB0_MAP (0x0178 - MX3FB_REG_OFFSET)
88 #define DI_DISP1_DB1_MAP (0x017C - MX3FB_REG_OFFSET)
89 #define DI_DISP1_DB2_MAP (0x0180 - MX3FB_REG_OFFSET)
90 #define DI_DISP1_CB0_MAP (0x0184 - MX3FB_REG_OFFSET)
91 #define DI_DISP1_CB1_MAP (0x0188 - MX3FB_REG_OFFSET)
92 #define DI_DISP1_CB2_MAP (0x018C - MX3FB_REG_OFFSET)
93 #define DI_DISP2_DB0_MAP (0x0190 - MX3FB_REG_OFFSET)
94 #define DI_DISP2_DB1_MAP (0x0194 - MX3FB_REG_OFFSET)
95 #define DI_DISP2_DB2_MAP (0x0198 - MX3FB_REG_OFFSET)
96 #define DI_DISP2_CB0_MAP (0x019C - MX3FB_REG_OFFSET)
97 #define DI_DISP2_CB1_MAP (0x01A0 - MX3FB_REG_OFFSET)
98 #define DI_DISP2_CB2_MAP (0x01A4 - MX3FB_REG_OFFSET)
99 #define DI_DISP3_B0_MAP (0x01A8 - MX3FB_REG_OFFSET)
100 #define DI_DISP3_B1_MAP (0x01AC - MX3FB_REG_OFFSET)
101 #define DI_DISP3_B2_MAP (0x01B0 - MX3FB_REG_OFFSET)
102 #define DI_DISP_ACC_CC (0x01B4 - MX3FB_REG_OFFSET)
103 #define DI_DISP_LLA_CONF (0x01B8 - MX3FB_REG_OFFSET)
104 #define DI_DISP_LLA_DATA (0x01BC - MX3FB_REG_OFFSET)