Lines Matching defs:mx3fb
32 #include <mach/mx3fb.h>
250 struct mx3fb_data *mx3fb;
264 struct mx3fb_data *mx3fb;
279 static u32 mx3fb_read_reg(struct mx3fb_data *mx3fb, unsigned long reg)
281 return __raw_readl(mx3fb->reg_base + reg);
284 static void mx3fb_write_reg(struct mx3fb_data *mx3fb, u32 value, unsigned long reg)
286 __raw_writel(value, mx3fb->reg_base + reg);
298 struct mx3fb_data *mx3fb = fbi->mx3fb;
301 reg = mx3fb_read_reg(mx3fb, SDC_COM_CONF);
303 mx3fb_write_reg(mx3fb, reg | SDC_COM_BG_EN, SDC_COM_CONF);
309 struct mx3fb_data *mx3fb = fbi->mx3fb;
312 reg = mx3fb_read_reg(mx3fb, SDC_COM_CONF);
314 mx3fb_write_reg(mx3fb, reg & ~SDC_COM_BG_EN, SDC_COM_CONF);
321 struct mx3fb_data *mx3fb = mx3_fbi->mx3fb;
328 dev_dbg(mx3fb->dev, "mx3fbi %p, desc %p, sg %p\n", mx3_fbi,
331 dev_dbg(mx3fb->dev, "mx3fbi %p, txd = NULL\n", mx3_fbi);
338 dev_err(mx3fb->dev, "Cannot allocate descriptor on %d\n",
347 dev_dbg(mx3fb->dev, "%d: Submit %p #%d [%c]\n", __LINE__,
351 dev_err(mx3fb->dev, "Cannot enable channel %d\n",
359 dev_dbg(mx3fb->dev, "%d: Re-submit %p #%d [%c]\n", __LINE__,
364 spin_lock_irqsave(&mx3fb->lock, flags);
367 spin_unlock_irqrestore(&mx3fb->lock, flags);
380 struct mx3fb_data *mx3fb = mx3_fbi->mx3fb;
384 spin_lock_irqsave(&mx3fb->lock, flags);
388 spin_unlock_irqrestore(&mx3fb->lock, flags);
398 * @mx3fb: mx3fb context.
404 static int sdc_set_window_pos(struct mx3fb_data *mx3fb, enum ipu_channel channel,
410 x_pos += mx3fb->h_start_width;
411 y_pos += mx3fb->v_start_width;
413 mx3fb_write_reg(mx3fb, (x_pos << 16) | y_pos, SDC_BG_POS);
419 * @mx3fb: mx3fb context.
438 static int sdc_init_panel(struct mx3fb_data *mx3fb, enum ipu_panel panel,
453 dev_dbg(mx3fb->dev, "panel size = %d x %d", width, height);
461 mx3fb_write_reg(mx3fb, reg, SDC_HOR_CONF);
469 mx3fb_write_reg(mx3fb, reg, SDC_VER_CONF);
475 mx3fb->h_start_width = h_start_width;
476 mx3fb->v_start_width = v_start_width;
480 mx3fb_write_reg(mx3fb, 0x00FD0102L, SDC_SHARP_CONF_1);
481 mx3fb_write_reg(mx3fb, 0x00F500F4L, SDC_SHARP_CONF_2);
482 mx3fb_write_reg(mx3fb, SDC_COM_SHARP | SDC_COM_TFT_COLOR, SDC_COM_CONF);
485 mx3fb_write_reg(mx3fb, SDC_COM_TFT_COLOR, SDC_COM_CONF);
498 ipu_clk = clk_get(mx3fb->dev, NULL);
507 dev_dbg(mx3fb->dev,
512 dev_dbg(mx3fb->dev, "pixel clk = %u, divider %u.%u\n",
515 spin_lock_irqsave(&mx3fb->lock, lock_flags);
522 mx3fb_write_reg(mx3fb, (((div / 8) - 1) << 22) | div, DI_DISP3_TIME_CONF);
525 old_conf = mx3fb_read_reg(mx3fb, DI_DISP_IF_CONF) & 0x78FFFFFF;
529 mx3fb_write_reg(mx3fb, old_conf, DI_DISP_IF_CONF);
531 old_conf = mx3fb_read_reg(mx3fb, DI_DISP_SIG_POL) & 0xE0FFFFFF;
537 mx3fb_write_reg(mx3fb, old_conf, DI_DISP_SIG_POL);
541 mx3fb_write_reg(mx3fb, di_mappings[0], DI_DISP3_B0_MAP);
542 mx3fb_write_reg(mx3fb, di_mappings[1], DI_DISP3_B1_MAP);
543 mx3fb_write_reg(mx3fb, di_mappings[2], DI_DISP3_B2_MAP);
544 mx3fb_write_reg(mx3fb, mx3fb_read_reg(mx3fb, DI_DISP_ACC_CC) |
548 mx3fb_write_reg(mx3fb, di_mappings[4], DI_DISP3_B0_MAP);
549 mx3fb_write_reg(mx3fb, di_mappings[5], DI_DISP3_B1_MAP);
550 mx3fb_write_reg(mx3fb, di_mappings[6], DI_DISP3_B2_MAP);
551 mx3fb_write_reg(mx3fb, mx3fb_read_reg(mx3fb, DI_DISP_ACC_CC) |
555 mx3fb_write_reg(mx3fb, di_mappings[8], DI_DISP3_B0_MAP);
556 mx3fb_write_reg(mx3fb, di_mappings[9], DI_DISP3_B1_MAP);
557 mx3fb_write_reg(mx3fb, di_mappings[10], DI_DISP3_B2_MAP);
558 mx3fb_write_reg(mx3fb, mx3fb_read_reg(mx3fb, DI_DISP_ACC_CC) |
562 mx3fb_write_reg(mx3fb, di_mappings[12], DI_DISP3_B0_MAP);
563 mx3fb_write_reg(mx3fb, di_mappings[13], DI_DISP3_B1_MAP);
564 mx3fb_write_reg(mx3fb, di_mappings[14], DI_DISP3_B2_MAP);
565 mx3fb_write_reg(mx3fb, mx3fb_read_reg(mx3fb, DI_DISP_ACC_CC) |
570 spin_unlock_irqrestore(&mx3fb->lock, lock_flags);
572 dev_dbg(mx3fb->dev, "DI_DISP_IF_CONF = 0x%08X\n",
573 mx3fb_read_reg(mx3fb, DI_DISP_IF_CONF));
574 dev_dbg(mx3fb->dev, "DI_DISP_SIG_POL = 0x%08X\n",
575 mx3fb_read_reg(mx3fb, DI_DISP_SIG_POL));
576 dev_dbg(mx3fb->dev, "DI_DISP3_TIME_CONF = 0x%08X\n",
577 mx3fb_read_reg(mx3fb, DI_DISP3_TIME_CONF));
584 * @mx3fb: mx3fb context.
590 static int sdc_set_color_key(struct mx3fb_data *mx3fb, enum ipu_channel channel,
596 spin_lock_irqsave(&mx3fb->lock, lock_flags);
598 sdc_conf = mx3fb_read_reg(mx3fb, SDC_COM_CONF);
605 reg = mx3fb_read_reg(mx3fb, SDC_GW_CTRL) & 0xFF000000L;
606 mx3fb_write_reg(mx3fb, reg | (color_key & 0x00FFFFFFL),
613 mx3fb_write_reg(mx3fb, sdc_conf, SDC_COM_CONF);
615 spin_unlock_irqrestore(&mx3fb->lock, lock_flags);
622 * @mx3fb: mx3fb context.
628 static int sdc_set_global_alpha(struct mx3fb_data *mx3fb, bool enable, uint8_t alpha)
633 spin_lock_irqsave(&mx3fb->lock, lock_flags);
636 reg = mx3fb_read_reg(mx3fb, SDC_GW_CTRL) & 0x00FFFFFFL;
637 mx3fb_write_reg(mx3fb, reg | ((uint32_t) alpha << 24), SDC_GW_CTRL);
639 reg = mx3fb_read_reg(mx3fb, SDC_COM_CONF);
640 mx3fb_write_reg(mx3fb, reg | SDC_COM_GLB_A, SDC_COM_CONF);
642 reg = mx3fb_read_reg(mx3fb, SDC_COM_CONF);
643 mx3fb_write_reg(mx3fb, reg & ~SDC_COM_GLB_A, SDC_COM_CONF);
646 spin_unlock_irqrestore(&mx3fb->lock, lock_flags);
651 static void sdc_set_brightness(struct mx3fb_data *mx3fb, uint8_t value)
653 dev_dbg(mx3fb->dev, "%s: value = %d\n", __func__, value);
655 mx3fb_write_reg(mx3fb, 0x03000000UL | value << 16, SDC_PWM_CTRL);
709 struct mx3fb_data *mx3fb = ichannel->client;
710 struct mx3fb_info *mx3_fbi = mx3fb->fbi->par;
712 dev_dbg(mx3fb->dev, "irq %d callback\n", ichannel->eof_irq);
726 struct mx3fb_data *mx3fb = mx3_fbi->mx3fb;
776 if (sdc_init_panel(mx3fb, mode,
790 "mx3fb: Error initializing panel.\n");
795 sdc_set_window_pos(mx3fb, mx3_fbi->ipu_ch, 0, 0);
818 struct mx3fb_data *mx3fb = mx3_fbi->mx3fb;
822 dev_dbg(mx3fb->dev, "%s [%c]\n", __func__, list_empty(&ichan->queue) ? '-' : '+');
987 struct mx3fb_data *mx3fb = mx3_fbi->mx3fb;
996 sdc_set_brightness(mx3fb, 0);
1004 sdc_set_brightness(mx3fb, mx3fb->backlight_level);
1118 * Emulate original mx3fb behaviour: each new call to idmac_tx_submit()
1176 struct mx3fb_data *mx3fb = platform_get_drvdata(pdev);
1177 struct mx3fb_info *mx3_fbi = mx3fb->fbi->par;
1180 fb_set_suspend(mx3fb->fbi, 1);
1185 sdc_set_brightness(mx3fb, 0);
1196 struct mx3fb_data *mx3fb = platform_get_drvdata(pdev);
1197 struct mx3fb_info *mx3_fbi = mx3fb->fbi->par;
1201 sdc_set_brightness(mx3fb, mx3fb->backlight_level);
1205 fb_set_suspend(mx3fb->fbi, 0);
1327 static int init_fb_chan(struct mx3fb_data *mx3fb, struct idmac_channel *ichan)
1329 struct device *dev = mx3fb->dev;
1338 ichan->client = mx3fb;
1375 mx3fb->fbi = fbi;
1378 mx3fb_write_reg(mx3fb, 0x00100010L, DI_HSP_CLK_PER);
1381 sdc_set_brightness(mx3fb, 255);
1382 sdc_set_global_alpha(mx3fb, true, 0xFF);
1383 sdc_set_color_key(mx3fb, IDMAC_SDC_0, false, 0);
1388 mx3fbi->mx3fb = mx3fb;
1393 dev_dbg(mx3fb->dev, "disabling irq %d\n", ichan->eof_irq);
1426 dev = rq->mx3fb->dev;
1448 struct mx3fb_data *mx3fb;
1461 mx3fb = kzalloc(sizeof(*mx3fb), GFP_KERNEL);
1462 if (!mx3fb)
1465 spin_lock_init(&mx3fb->lock);
1467 mx3fb->reg_base = ioremap(sdc_reg->start, resource_size(sdc_reg));
1468 if (!mx3fb->reg_base) {
1474 mx3fb->reg_base);
1479 mx3fb->dev = dev;
1480 platform_set_drvdata(pdev, mx3fb);
1482 rq.mx3fb = mx3fb;
1494 mx3fb->backlight_level = 255;
1496 ret = init_fb_chan(mx3fb, to_idmac_chan(chan));
1506 iounmap(mx3fb->reg_base);
1508 kfree(mx3fb);
1509 dev_err(dev, "mx3fb: failed to register fb\n");
1515 struct mx3fb_data *mx3fb = platform_get_drvdata(dev);
1516 struct fb_info *fbi = mx3fb->fbi;
1526 iounmap(mx3fb->reg_base);
1527 kfree(mx3fb);
1542 * Parse user specified options (`video=mx3fb:')
1544 * video=mx3fb:bpp=16
1551 if (fb_get_options("mx3fb", &options))