Lines Matching refs:minfo
92 void matroxfb_DAC_out(const struct matrox_fb_info *minfo, int reg, int val)
99 int matroxfb_DAC_in(const struct matrox_fb_info *minfo, int reg)
189 int matroxfb_vgaHWinit(struct matrox_fb_info *minfo, struct my_timming *m)
196 struct matrox_hw_state * const hw = &minfo->hw;
246 divider = minfo->curr.final_bppShift;
276 wd = minfo->fbcon.var.xres_virtual * minfo->curr.final_bppShift / 64;
292 if (minfo->outputs[1].src == MATROXFB_SRC_CRTC1)
336 void matroxfb_vgaHWrestore(struct matrox_fb_info *minfo)
339 struct matrox_hw_state * const hw = &minfo->hw;
528 static int parse_pins1(struct matrox_fb_info *minfo,
541 minfo->limits.pixel.vcomax = maxdac;
542 minfo->values.pll.system = get_unaligned_le16(bd->pins + 28) ?
545 minfo->features.pll.ref_freq = 14318;
546 minfo->values.reg.mctlwtst = 0x00030101;
550 static void default_pins1(struct matrox_fb_info *minfo)
553 minfo->limits.pixel.vcomax = 220000;
554 minfo->values.pll.system = 50000;
555 minfo->features.pll.ref_freq = 14318;
556 minfo->values.reg.mctlwtst = 0x00030101;
559 static int parse_pins2(struct matrox_fb_info *minfo,
562 minfo->limits.pixel.vcomax =
563 minfo->limits.system.vcomax = (bd->pins[41] == 0xFF) ? 230000 : ((bd->pins[41] + 100) * 1000);
564 minfo->values.reg.mctlwtst = ((bd->pins[51] & 0x01) ? 0x00000001 : 0) |
568 minfo->values.pll.system = (bd->pins[43] == 0xFF) ? 50000 : ((bd->pins[43] + 100) * 1000);
569 minfo->features.pll.ref_freq = 14318;
573 static void default_pins2(struct matrox_fb_info *minfo)
576 minfo->limits.pixel.vcomax =
577 minfo->limits.system.vcomax = 230000;
578 minfo->values.reg.mctlwtst = 0x00030101;
579 minfo->values.pll.system = 50000;
580 minfo->features.pll.ref_freq = 14318;
583 static int parse_pins3(struct matrox_fb_info *minfo,
586 minfo->limits.pixel.vcomax =
587 minfo->limits.system.vcomax = (bd->pins[36] == 0xFF) ? 230000 : ((bd->pins[36] + 100) * 1000);
588 minfo->values.reg.mctlwtst = get_unaligned_le32(bd->pins + 48) == 0xFFFFFFFF ?
591 minfo->values.reg.memrdbk = ((bd->pins[57] << 21) & 0x1E000000) |
595 minfo->values.reg.opt = (bd->pins[54] & 7) << 10;
596 minfo->values.reg.opt2 = bd->pins[58] << 12;
597 minfo->features.pll.ref_freq = (bd->pins[52] & 0x20) ? 14318 : 27000;
601 static void default_pins3(struct matrox_fb_info *minfo)
604 minfo->limits.pixel.vcomax =
605 minfo->limits.system.vcomax = 230000;
606 minfo->values.reg.mctlwtst = 0x01250A21;
607 minfo->values.reg.memrdbk = 0x00000000;
608 minfo->values.reg.opt = 0x00000C00;
609 minfo->values.reg.opt2 = 0x00000000;
610 minfo->features.pll.ref_freq = 27000;
613 static int parse_pins4(struct matrox_fb_info *minfo,
616 minfo->limits.pixel.vcomax = (bd->pins[ 39] == 0xFF) ? 230000 : bd->pins[ 39] * 4000;
617 minfo->limits.system.vcomax = (bd->pins[ 38] == 0xFF) ? minfo->limits.pixel.vcomax : bd->pins[ 38] * 4000;
618 minfo->values.reg.mctlwtst = get_unaligned_le32(bd->pins + 71);
619 minfo->values.reg.memrdbk = ((bd->pins[87] << 21) & 0x1E000000) |
623 minfo->values.reg.opt = ((bd->pins[53] << 15) & 0x00400000) |
626 minfo->values.reg.opt3 = get_unaligned_le32(bd->pins + 67);
627 minfo->values.pll.system = (bd->pins[ 65] == 0xFF) ? 200000 : bd->pins[ 65] * 4000;
628 minfo->features.pll.ref_freq = (bd->pins[ 92] & 0x01) ? 14318 : 27000;
632 static void default_pins4(struct matrox_fb_info *minfo)
635 minfo->limits.pixel.vcomax =
636 minfo->limits.system.vcomax = 252000;
637 minfo->values.reg.mctlwtst = 0x04A450A1;
638 minfo->values.reg.memrdbk = 0x000000E7;
639 minfo->values.reg.opt = 0x10000400;
640 minfo->values.reg.opt3 = 0x0190A419;
641 minfo->values.pll.system = 200000;
642 minfo->features.pll.ref_freq = 27000;
645 static int parse_pins5(struct matrox_fb_info *minfo,
652 minfo->limits.pixel.vcomax = (bd->pins[ 38] == 0xFF) ? 600000 : bd->pins[ 38] * mult;
653 minfo->limits.system.vcomax = (bd->pins[ 36] == 0xFF) ? minfo->limits.pixel.vcomax : bd->pins[ 36] * mult;
654 minfo->limits.video.vcomax = (bd->pins[ 37] == 0xFF) ? minfo->limits.system.vcomax : bd->pins[ 37] * mult;
655 minfo->limits.pixel.vcomin = (bd->pins[123] == 0xFF) ? 256000 : bd->pins[123] * mult;
656 minfo->limits.system.vcomin = (bd->pins[121] == 0xFF) ? minfo->limits.pixel.vcomin : bd->pins[121] * mult;
657 minfo->limits.video.vcomin = (bd->pins[122] == 0xFF) ? minfo->limits.system.vcomin : bd->pins[122] * mult;
658 minfo->values.pll.system =
659 minfo->values.pll.video = (bd->pins[ 92] == 0xFF) ? 284000 : bd->pins[ 92] * 4000;
660 minfo->values.reg.opt = get_unaligned_le32(bd->pins + 48);
661 minfo->values.reg.opt2 = get_unaligned_le32(bd->pins + 52);
662 minfo->values.reg.opt3 = get_unaligned_le32(bd->pins + 94);
663 minfo->values.reg.mctlwtst = get_unaligned_le32(bd->pins + 98);
664 minfo->values.reg.memmisc = get_unaligned_le32(bd->pins + 102);
665 minfo->values.reg.memrdbk = get_unaligned_le32(bd->pins + 106);
666 minfo->features.pll.ref_freq = (bd->pins[110] & 0x01) ? 14318 : 27000;
667 minfo->values.memory.ddr = (bd->pins[114] & 0x60) == 0x20;
668 minfo->values.memory.dll = (bd->pins[115] & 0x02) != 0;
669 minfo->values.memory.emrswen = (bd->pins[115] & 0x01) != 0;
670 minfo->values.reg.maccess = minfo->values.memory.emrswen ? 0x00004000 : 0x00000000;
672 minfo->values.reg.mctlwtst_core = minfo->values.reg.mctlwtst;
675 minfo->values.reg.mctlwtst_core = (minfo->values.reg.mctlwtst & ~7) |
676 wtst_xlat[minfo->values.reg.mctlwtst & 7];
678 minfo->max_pixel_clock_panellink = bd->pins[47] * 4000;
682 static void default_pins5(struct matrox_fb_info *minfo)
685 minfo->limits.pixel.vcomax =
686 minfo->limits.system.vcomax =
687 minfo->limits.video.vcomax = 600000;
688 minfo->limits.pixel.vcomin =
689 minfo->limits.system.vcomin =
690 minfo->limits.video.vcomin = 256000;
691 minfo->values.pll.system =
692 minfo->values.pll.video = 284000;
693 minfo->values.reg.opt = 0x404A1160;
694 minfo->values.reg.opt2 = 0x0000AC00;
695 minfo->values.reg.opt3 = 0x0090A409;
696 minfo->values.reg.mctlwtst_core =
697 minfo->values.reg.mctlwtst = 0x0C81462B;
698 minfo->values.reg.memmisc = 0x80000004;
699 minfo->values.reg.memrdbk = 0x01001103;
700 minfo->features.pll.ref_freq = 27000;
701 minfo->values.memory.ddr = 1;
702 minfo->values.memory.dll = 1;
703 minfo->values.memory.emrswen = 1;
704 minfo->values.reg.maccess = 0x00004000;
707 static int matroxfb_set_limits(struct matrox_fb_info *minfo,
713 switch (minfo->chip) {
714 case MGA_2064: default_pins1(minfo); break;
717 case MGA_1164: default_pins2(minfo); break;
719 case MGA_G200: default_pins3(minfo); break;
720 case MGA_G400: default_pins4(minfo); break;
722 case MGA_G550: default_pins5(minfo); break;
747 return parse_pins1(minfo, bd);
749 return parse_pins2(minfo, bd);
751 return parse_pins3(minfo, bd);
753 return parse_pins4(minfo, bd);
755 return parse_pins5(minfo, bd);
762 void matroxfb_read_pins(struct matrox_fb_info *minfo)
767 struct pci_dev *pdev = minfo->pcidev;
769 memset(&minfo->bios, 0, sizeof(minfo->bios));
773 pci_read_config_dword(pdev, minfo->devflags.fbResource, &fbbase);
775 parse_bios(vaddr_va(minfo->video.vbase), &minfo->bios);
779 if (!minfo->bios.bios_valid) {
793 parse_bios(b, &minfo->bios);
799 matroxfb_set_limits(minfo, &minfo->bios);
801 (minfo->values.reg.opt & 0x1C00) >> 10);