Lines Matching refs:hw
302 struct matrox_hw_state *hw = &minfo->hw;
308 hw->DACclk[0] = pixin | 0xC0;
309 hw->DACclk[1] = pixfeed;
310 hw->DACclk[2] = pixpost | 0xB0;
338 hw->DACclk[3] = ((65 - loopin) & 0x3F) | 0xC0;
339 hw->DACclk[4] = (65 - loopfeed) | 0x80;
342 hw->DACreg[POS3026_XLATCHCTRL] = TVP3026B_XLATCHCTRL_8_3;
344 hw->DACclk[4] &= ~0xC0;
345 hw->DACreg[POS3026_XLATCHCTRL] = TVP3026B_XLATCHCTRL_4_3;
351 hw->DACclk[4] ^= 0xC0; /* change from 0x80 to 0x40 */
352 hw->DACreg[POS3026_XLATCHCTRL] = TVP3026A_XLATCHCTRL_4_3;
355 hw->DACclk[5] = looppost | 0xF8;
357 hw->DACclk[5] ^= 0x40;
359 hw->DACclk[3] = ((65 - loopin) & 0x3F) | 0xC0;
360 hw->DACclk[4] = 65 - loopfeed;
361 hw->DACclk[5] = looppost | 0xF0;
363 hw->DACreg[POS3026_XMEMPLLCTRL] = loopdiv | TVP3026_XMEMPLLCTRL_MCLK_MCLKPLL | TVP3026_XMEMPLLCTRL_RCLK_LOOPPLL;
371 struct matrox_hw_state *hw = &minfo->hw;
375 memcpy(hw->DACreg, MGADACbpp32, sizeof(hw->DACreg));
377 case 4: hw->DACreg[POS3026_XLATCHCTRL] = TVP3026_XLATCHCTRL_16_1; /* or _8_1, they are same */
378 hw->DACreg[POS3026_XTRUECOLORCTRL] = TVP3026_XTRUECOLORCTRL_PSEUDOCOLOR;
379 hw->DACreg[POS3026_XMUXCTRL] = muxctrl | TVP3026_XMUXCTRL_PIXEL_4BIT;
380 hw->DACreg[POS3026_XCLKCTRL] = TVP3026_XCLKCTRL_SRC_PLL | TVP3026_XCLKCTRL_DIV8;
381 hw->DACreg[POS3026_XMISCCTRL] = TVP3026_XMISCCTRL_DAC_PUP | TVP3026_XMISCCTRL_DAC_8BIT | TVP3026_XMISCCTRL_PSEL_DIS | TVP3026_XMISCCTRL_PSEL_LOW;
383 case 8: hw->DACreg[POS3026_XLATCHCTRL] = TVP3026_XLATCHCTRL_8_1; /* or _4_1, they are same */
384 hw->DACreg[POS3026_XTRUECOLORCTRL] = TVP3026_XTRUECOLORCTRL_PSEUDOCOLOR;
385 hw->DACreg[POS3026_XMUXCTRL] = muxctrl | TVP3026_XMUXCTRL_PIXEL_8BIT;
386 hw->DACreg[POS3026_XCLKCTRL] = TVP3026_XCLKCTRL_SRC_PLL | TVP3026_XCLKCTRL_DIV4;
387 hw->DACreg[POS3026_XMISCCTRL] = TVP3026_XMISCCTRL_DAC_PUP | TVP3026_XMISCCTRL_DAC_8BIT | TVP3026_XMISCCTRL_PSEL_DIS | TVP3026_XMISCCTRL_PSEL_LOW;
391 hw->DACreg[POS3026_XTRUECOLORCTRL] = (minfo->fbcon.var.green.length == 5) ? (TVP3026_XTRUECOLORCTRL_DIRECTCOLOR | TVP3026_XTRUECOLORCTRL_ORGB_1555) : (TVP3026_XTRUECOLORCTRL_DIRECTCOLOR | TVP3026_XTRUECOLORCTRL_RGB_565);
392 hw->DACreg[POS3026_XMUXCTRL] = muxctrl | TVP3026_XMUXCTRL_PIXEL_16BIT;
393 hw->DACreg[POS3026_XCLKCTRL] = TVP3026_XCLKCTRL_SRC_PLL | TVP3026_XCLKCTRL_DIV2;
397 hw->DACreg[POS3026_XTRUECOLORCTRL] = TVP3026_XTRUECOLORCTRL_DIRECTCOLOR | TVP3026_XTRUECOLORCTRL_RGB_888;
398 hw->DACreg[POS3026_XMUXCTRL] = muxctrl | TVP3026_XMUXCTRL_PIXEL_32BIT;
399 hw->DACreg[POS3026_XCLKCTRL] = TVP3026_XCLKCTRL_SRC_PLL | TVP3026_XCLKCTRL_DIV4;
403 hw->DACreg[POS3026_XMUXCTRL] = muxctrl | TVP3026_XMUXCTRL_PIXEL_32BIT;
411 hw->MiscOutReg = 0xCB;
413 hw->DACreg[POS3026_XGENCTRL] |= TVP3026_XGENCTRL_HSYNC_NEG;
415 hw->DACreg[POS3026_XGENCTRL] |= TVP3026_XGENCTRL_VSYNC_NEG;
417 hw->DACreg[POS3026_XGENCTRL] |= TVP3026_XGENCTRL_SYNC_ON_GREEN;
421 hw->CRTCEXT[3] |= 0x08;
423 hw->CRTCEXT[3] |= 0x10;
427 hw->DACreg[POS3026_XCURCTRL] |= TVP3026_XCURCTRL_INTERLACED;
430 hw->DACreg[POS3026_XCURCTRL] |= TVP3026_XCURCTRL_BLANK4096;
433 hw->MXoptionReg &= ~0x00001000;
434 if (isInterleave(minfo)) hw->MXoptionReg |= 0x00001000;
514 minfo->hw.MXoptionReg = (minfo->hw.MXoptionReg & ~0x000F0000) | (rfhcnt << 16);
515 pci_write_config_dword(minfo->pcidev, PCI_OPTION_REG, minfo->hw.MXoptionReg);
561 struct matrox_hw_state *hw = &minfo->hw;
569 dprintk("%02X:", hw->CRTCEXT[i]);
575 pci_write_config_dword(minfo->pcidev, PCI_OPTION_REG, hw->MXoptionReg);
585 mga_setr(M_EXTVGA_INDEX, i, hw->CRTCEXT[i]);
588 outTi3026(minfo, DACseq[i], hw->DACreg[i]);
602 if (memcmp(hw->DACclk, progdac, 6)) {
608 outTi3026(minfo, TVP3026_XCLKCTRL, hw->DACreg[POS3026_XCLKCTRL]);
615 outTi3026(minfo, TVP3026_XPIXPLLDATA, hw->DACclk[i]);
617 if (hw->MiscOutReg & 0x08) {
634 outTi3026(minfo, TVP3026_XMEMPLLCTRL, hw->DACreg[POS3026_XMEMPLLCTRL]);
637 outTi3026(minfo, TVP3026_XLOOPPLLDATA, hw->DACclk[i]);
639 if ((hw->MiscOutReg & 0x08) && ((hw->DACclk[5] & 0x80) == 0x80)) {
660 dprintk("R%02X=%02X ", DACseq[i], hw->DACreg[i]);
665 dprintk("C%02X=%02X ", i, hw->DACclk[i]);
689 struct matrox_hw_state *hw = &minfo->hw;
707 hw->MXoptionReg &= 0xC0000100;
708 hw->MXoptionReg |= 0x002C0000;
710 hw->MXoptionReg &= ~0x00000100;
712 hw->MXoptionReg &= ~0x40000000;
714 hw->MXoptionReg |= 0x20000000;
715 pci_write_config_dword(minfo->pcidev, PCI_OPTION_REG, hw->MXoptionReg);