Lines Matching refs:minfo
36 static void DAC1064_calcclock(const struct matrox_fb_info *minfo,
48 fvco = PLL_calcclock(minfo, freq, fmax, in, feed, &p);
87 static void DAC1064_setpclk(struct matrox_fb_info *minfo, unsigned long fout)
93 DAC1064_calcclock(minfo, fout, minfo->max_pixel_clock, &m, &n, &p);
94 minfo->hw.DACclk[0] = m;
95 minfo->hw.DACclk[1] = n;
96 minfo->hw.DACclk[2] = p;
99 static void DAC1064_setmclk(struct matrox_fb_info *minfo, int oscinfo,
103 struct matrox_hw_state *hw = &minfo->hw;
107 if (minfo->devflags.noinit) {
109 hw->DACclk[3] = inDAC1064(minfo, DAC1064_XSYSPLLM);
110 hw->DACclk[4] = inDAC1064(minfo, DAC1064_XSYSPLLN);
111 hw->DACclk[5] = inDAC1064(minfo, DAC1064_XSYSPLLP);
115 pci_write_config_dword(minfo->pcidev, PCI_OPTION_REG, mx);
130 pci_write_config_dword(minfo->pcidev, PCI_OPTION_REG, mx);
132 pci_write_config_dword(minfo->pcidev, PCI_OPTION_REG, mx);
141 DAC1064_calcclock(minfo, fmem, minfo->max_pixel_clock, &m, &n, &p);
142 outDAC1064(minfo, DAC1064_XSYSPLLM, hw->DACclk[3] = m);
143 outDAC1064(minfo, DAC1064_XSYSPLLN, hw->DACclk[4] = n);
144 outDAC1064(minfo, DAC1064_XSYSPLLP, hw->DACclk[5] = p);
146 if (inDAC1064(minfo, DAC1064_XSYSPLLSTAT) & 0x40)
157 pci_write_config_dword(minfo->pcidev, PCI_OPTION_REG, mx);
159 pci_write_config_dword(minfo->pcidev, PCI_OPTION_REG, mx);
164 static void g450_set_plls(struct matrox_fb_info *minfo)
168 struct matrox_hw_state *hw = &minfo->hw;
175 pixelmnp = minfo->crtc1.mnp;
176 videomnp = minfo->crtc2.mnp;
180 } else if (minfo->crtc2.pixclock == minfo->features.pll.ref_freq) {
195 outDAC1064(minfo, M1064_XPWRCTRL, hw->DACreg[POS1064_XPWRCTRL]);
196 matroxfb_g450_setpll_cond(minfo, videomnp, M_VIDEO_PLL);
203 outDAC1064(minfo, M1064_XPIXCLKCTRL, hw->DACreg[POS1064_XPIXCLKCTRL]);
204 matroxfb_g450_setpll_cond(minfo, pixelmnp, M_PIXEL_PLL_C);
211 pxc = minfo->crtc1.pixclock;
212 if (pxc == 0 || minfo->outputs[2].src == MATROXFB_SRC_CRTC2) {
213 pxc = minfo->crtc2.pixclock;
215 if (minfo->chip == MGA_G550) {
256 void DAC1064_global_init(struct matrox_fb_info *minfo)
258 struct matrox_hw_state *hw = &minfo->hw;
264 if (minfo->devflags.g450dac) {
268 switch (minfo->outputs[0].src) {
277 switch (minfo->outputs[1].src) {
282 if (minfo->outputs[1].mode == MATROXFB_OUTPUT_MODE_MONITOR) {
292 switch (minfo->outputs[2].src) {
303 g450_set_plls(minfo);
307 if (minfo->outputs[1].src == MATROXFB_SRC_CRTC1) {
310 } else if (minfo->outputs[1].src == MATROXFB_SRC_CRTC2) {
312 } else if (minfo->outputs[2].src == MATROXFB_SRC_CRTC1)
317 if (minfo->outputs[0].src != MATROXFB_SRC_NONE)
322 void DAC1064_global_restore(struct matrox_fb_info *minfo)
324 struct matrox_hw_state *hw = &minfo->hw;
326 outDAC1064(minfo, M1064_XPIXCLKCTRL, hw->DACreg[POS1064_XPIXCLKCTRL]);
327 outDAC1064(minfo, M1064_XMISCCTRL, hw->DACreg[POS1064_XMISCCTRL]);
328 if (minfo->devflags.accelerator == FB_ACCEL_MATROX_MGAG400) {
329 outDAC1064(minfo, 0x20, 0x04);
330 outDAC1064(minfo, 0x1F, minfo->devflags.dfp_type);
331 if (minfo->devflags.g450dac) {
332 outDAC1064(minfo, M1064_XSYNCCTRL, 0xCC);
333 outDAC1064(minfo, M1064_XPWRCTRL, hw->DACreg[POS1064_XPWRCTRL]);
334 outDAC1064(minfo, M1064_XPANMODE, hw->DACreg[POS1064_XPANMODE]);
335 outDAC1064(minfo, M1064_XOUTPUTCONN, hw->DACreg[POS1064_XOUTPUTCONN]);
340 static int DAC1064_init_1(struct matrox_fb_info *minfo, struct my_timming *m)
342 struct matrox_hw_state *hw = &minfo->hw;
347 switch (minfo->fbcon.var.bits_per_pixel) {
353 if (minfo->fbcon.var.green.length == 5)
367 hw->DACreg[POS1064_XVREFCTRL] = minfo->features.DAC1064.xvrefctrl;
373 DAC1064_global_init(minfo);
377 static int DAC1064_init_2(struct matrox_fb_info *minfo, struct my_timming *m)
379 struct matrox_hw_state *hw = &minfo->hw;
383 if (minfo->fbcon.var.bits_per_pixel > 16) { /* 256 entries */
391 } else if (minfo->fbcon.var.bits_per_pixel > 8) {
392 if (minfo->fbcon.var.green.length == 5) { /* 0..31, 128..159 */
420 static void DAC1064_restore_1(struct matrox_fb_info *minfo)
422 struct matrox_hw_state *hw = &minfo->hw;
430 if ((inDAC1064(minfo, DAC1064_XSYSPLLM) != hw->DACclk[3]) ||
431 (inDAC1064(minfo, DAC1064_XSYSPLLN) != hw->DACclk[4]) ||
432 (inDAC1064(minfo, DAC1064_XSYSPLLP) != hw->DACclk[5])) {
433 outDAC1064(minfo, DAC1064_XSYSPLLM, hw->DACclk[3]);
434 outDAC1064(minfo, DAC1064_XSYSPLLN, hw->DACclk[4]);
435 outDAC1064(minfo, DAC1064_XSYSPLLP, hw->DACclk[5]);
442 outDAC1064(minfo, MGA1064_DAC_regs[i], hw->DACreg[i]);
446 DAC1064_global_restore(minfo);
451 static void DAC1064_restore_2(struct matrox_fb_info *minfo)
462 dprintk("R%02X=%02X ", MGA1064_DAC_regs[i], minfo->hw.DACreg[i]);
467 dprintk("C%02X=%02X ", i, minfo->hw.DACclk[i]);
473 #define minfo ((struct matrox_fb_info*)out)
479 DAC1064_setpclk(minfo, m->pixclock);
484 outDAC1064(minfo, M1064_XPIXPLLCM + i, minfo->hw.DACclk[i]);
486 if (inDAC1064(minfo, M1064_XPIXPLLSTAT) & 0x40)
496 #undef minfo
507 #define minfo ((struct matrox_fb_info*)out)
509 m->mnp = matroxfb_g450_setclk(minfo, m->pixclock, (m->crtc == MATROXFB_SRC_CRTC1) ? M_PIXEL_PLL_C : M_VIDEO_PLL);
511 m->pixclock = g450_mnp2f(minfo, m->mnp);
514 #undef minfo
527 static int MGA1064_init(struct matrox_fb_info *minfo, struct my_timming *m)
529 struct matrox_hw_state *hw = &minfo->hw;
533 if (DAC1064_init_1(minfo, m)) return 1;
534 if (matroxfb_vgaHWinit(minfo, m)) return 1;
544 if (DAC1064_init_2(minfo, m)) return 1;
550 static int MGAG100_init(struct matrox_fb_info *minfo, struct my_timming *m)
552 struct matrox_hw_state *hw = &minfo->hw;
556 if (DAC1064_init_1(minfo, m)) return 1;
558 if (matroxfb_vgaHWinit(minfo, m)) return 1;
568 if (DAC1064_init_2(minfo, m)) return 1;
574 static void MGA1064_ramdac_init(struct matrox_fb_info *minfo)
579 /* minfo->features.DAC1064.vco_freq_min = 120000; */
580 minfo->features.pll.vco_freq_min = 62000;
581 minfo->features.pll.ref_freq = 14318;
582 minfo->features.pll.feed_div_min = 100;
583 minfo->features.pll.feed_div_max = 127;
584 minfo->features.pll.in_div_min = 1;
585 minfo->features.pll.in_div_max = 31;
586 minfo->features.pll.post_shift_max = 3;
587 minfo->features.DAC1064.xvrefctrl = DAC1064_XVREFCTRL_EXTERNAL;
589 DAC1064_setmclk(minfo, DAC1064_OPT_MDIV2 | DAC1064_OPT_GDIV3 | DAC1064_OPT_SCLK_PLL, 133333);
598 static void MGAG100_progPixClock(const struct matrox_fb_info *minfo, int flags,
607 outDAC1064(minfo, M1064_XPIXCLKCTRL, inDAC1064(minfo, M1064_XPIXCLKCTRL) | M1064_XPIXCLKCTRL_DIS |
614 outDAC1064(minfo, reg++, m);
615 outDAC1064(minfo, reg++, n);
616 outDAC1064(minfo, reg, p);
628 if (inDAC1064(minfo, M1064_XPIXPLLSTAT) & 0x40)
634 selClk = inDAC1064(minfo, M1064_XPIXCLKCTRL) & ~M1064_XPIXCLKCTRL_SRC_MASK;
640 outDAC1064(minfo, M1064_XPIXCLKCTRL, selClk);
641 outDAC1064(minfo, M1064_XPIXCLKCTRL, inDAC1064(minfo, M1064_XPIXCLKCTRL) & ~M1064_XPIXCLKCTRL_DIS);
644 static void MGAG100_setPixClock(const struct matrox_fb_info *minfo, int flags,
651 DAC1064_calcclock(minfo, freq, minfo->max_pixel_clock, &m, &n, &p);
652 MGAG100_progPixClock(minfo, flags, m, n, p);
657 static int MGA1064_preinit(struct matrox_fb_info *minfo)
662 struct matrox_hw_state *hw = &minfo->hw;
666 /* minfo->capable.cfb4 = 0; ... preinitialized by 0 */
667 minfo->capable.text = 1;
668 minfo->capable.vxres = vxres_mystique;
670 minfo->outputs[0].output = &m1064;
671 minfo->outputs[0].src = minfo->outputs[0].default_src;
672 minfo->outputs[0].data = minfo;
673 minfo->outputs[0].mode = MATROXFB_OUTPUT_MODE_MONITOR;
675 if (minfo->devflags.noinit)
679 if (minfo->devflags.novga)
681 if (minfo->devflags.nobios)
683 if (minfo->devflags.nopciretry)
685 pci_write_config_dword(minfo->pcidev, PCI_OPTION_REG, hw->MXoptionReg);
695 static void MGA1064_reset(struct matrox_fb_info *minfo)
700 MGA1064_ramdac_init(minfo);
705 static void g450_mclk_init(struct matrox_fb_info *minfo)
708 pci_write_config_dword(minfo->pcidev, PCI_OPTION_REG, minfo->hw.MXoptionReg | 4);
709 pci_write_config_dword(minfo->pcidev, PCI_OPTION3_REG, minfo->values.reg.opt3 & ~0x00300C03);
710 pci_write_config_dword(minfo->pcidev, PCI_OPTION_REG, minfo->hw.MXoptionReg);
712 if (((minfo->values.reg.opt3 & 0x000003) == 0x000003) ||
713 ((minfo->values.reg.opt3 & 0x000C00) == 0x000C00) ||
714 ((minfo->values.reg.opt3 & 0x300000) == 0x300000)) {
715 matroxfb_g450_setclk(minfo, minfo->values.pll.video, M_VIDEO_PLL);
721 pwr = inDAC1064(minfo, M1064_XPWRCTRL) & ~0x02;
722 outDAC1064(minfo, M1064_XPWRCTRL, pwr);
725 matroxfb_g450_setclk(minfo, minfo->values.pll.system, M_SYSTEM_PLL);
728 pci_write_config_dword(minfo->pcidev, PCI_OPTION_REG, minfo->hw.MXoptionReg | 4);
729 pci_write_config_dword(minfo->pcidev, PCI_OPTION3_REG, minfo->values.reg.opt3);
730 pci_write_config_dword(minfo->pcidev, PCI_OPTION_REG, minfo->hw.MXoptionReg);
734 static void g450_memory_init(struct matrox_fb_info *minfo)
737 minfo->hw.MXoptionReg &= ~0x001F8000;
738 pci_write_config_dword(minfo->pcidev, PCI_OPTION_REG, minfo->hw.MXoptionReg);
741 minfo->hw.MXoptionReg &= ~0x00207E00;
742 minfo->hw.MXoptionReg |= 0x00207E00 & minfo->values.reg.opt;
743 pci_write_config_dword(minfo->pcidev, PCI_OPTION_REG, minfo->hw.MXoptionReg);
744 pci_write_config_dword(minfo->pcidev, PCI_OPTION2_REG, minfo->values.reg.opt2);
746 mga_outl(M_CTLWTST, minfo->values.reg.mctlwtst);
749 pci_write_config_dword(minfo->pcidev, PCI_MEMMISC_REG, minfo->values.reg.memmisc & ~0x80000000U);
750 mga_outl(M_MEMRDBK, minfo->values.reg.memrdbk);
751 mga_outl(M_MACCESS, minfo->values.reg.maccess);
753 pci_write_config_dword(minfo->pcidev, PCI_MEMMISC_REG, minfo->values.reg.memmisc | 0x80000000U);
757 if (minfo->values.memory.ddr && (!minfo->values.memory.emrswen || !minfo->values.memory.dll)) {
758 mga_outl(M_MEMRDBK, minfo->values.reg.memrdbk & ~0x1000);
760 mga_outl(M_MACCESS, minfo->values.reg.maccess | 0x8000);
764 minfo->hw.MXoptionReg |= 0x001F8000 & minfo->values.reg.opt;
765 pci_write_config_dword(minfo->pcidev, PCI_OPTION_REG, minfo->hw.MXoptionReg);
771 if (minfo->values.reg.mctlwtst != minfo->values.reg.mctlwtst_core) {
772 mga_outl(M_CTLWTST, minfo->values.reg.mctlwtst_core);
777 static void g450_preinit(struct matrox_fb_info *minfo)
783 /* minfo->hw.MXoptionReg = minfo->values.reg.opt; */
784 minfo->hw.MXoptionReg &= 0xC0000100;
785 minfo->hw.MXoptionReg |= 0x00000020;
786 if (minfo->devflags.novga)
787 minfo->hw.MXoptionReg &= ~0x00000100;
788 if (minfo->devflags.nobios)
789 minfo->hw.MXoptionReg &= ~0x40000000;
790 if (minfo->devflags.nopciretry)
791 minfo->hw.MXoptionReg |= 0x20000000;
792 minfo->hw.MXoptionReg |= minfo->values.reg.opt & 0x03400040;
793 pci_write_config_dword(minfo->pcidev, PCI_OPTION_REG, minfo->hw.MXoptionReg);
801 curctl = inDAC1064(minfo, M1064_XCURCTRL);
802 outDAC1064(minfo, M1064_XCURCTRL, 0);
807 g450_mclk_init(minfo);
808 g450_memory_init(minfo);
811 matroxfb_g450_setclk(minfo, 25175, M_PIXEL_PLL_A);
812 matroxfb_g450_setclk(minfo, 28322, M_PIXEL_PLL_B);
818 outDAC1064(minfo, M1064_XCURCTRL, curctl);
826 static int MGAG100_preinit(struct matrox_fb_info *minfo)
831 struct matrox_hw_state *hw = &minfo->hw;
838 if (minfo->devflags.g450dac) {
839 minfo->features.pll.vco_freq_min = 130000; /* my sample: >118 */
841 minfo->features.pll.vco_freq_min = 62000;
843 if (!minfo->features.pll.ref_freq) {
844 minfo->features.pll.ref_freq = 27000;
846 minfo->features.pll.feed_div_min = 7;
847 minfo->features.pll.feed_div_max = 127;
848 minfo->features.pll.in_div_min = 1;
849 minfo->features.pll.in_div_max = 31;
850 minfo->features.pll.post_shift_max = 3;
851 minfo->features.DAC1064.xvrefctrl = DAC1064_XVREFCTRL_G100_DEFAULT;
852 /* minfo->capable.cfb4 = 0; ... preinitialized by 0 */
853 minfo->capable.text = 1;
854 minfo->capable.vxres = vxres_g100;
855 minfo->capable.plnwt = minfo->devflags.accelerator == FB_ACCEL_MATROX_MGAG100
856 ? minfo->devflags.sgram : 1;
859 if (minfo->devflags.g450dac) {
860 minfo->outputs[0].output = &g450out;
864 minfo->outputs[0].output = &m1064;
866 minfo->outputs[0].src = minfo->outputs[0].default_src;
867 minfo->outputs[0].data = minfo;
868 minfo->outputs[0].mode = MATROXFB_OUTPUT_MODE_MONITOR;
870 if (minfo->devflags.g450dac) {
875 if (minfo->devflags.noinit)
877 if (minfo->devflags.g450dac) {
878 g450_preinit(minfo);
883 if (minfo->devflags.novga)
885 if (minfo->devflags.nobios)
887 if (minfo->devflags.nopciretry)
889 pci_write_config_dword(minfo->pcidev, PCI_OPTION_REG, hw->MXoptionReg);
890 DAC1064_setmclk(minfo, DAC1064_OPT_MDIV2 | DAC1064_OPT_GDIV3 | DAC1064_OPT_SCLK_PCI, 133333);
892 if (minfo->devflags.accelerator == FB_ACCEL_MATROX_MGAG100) {
893 pci_read_config_dword(minfo->pcidev, PCI_OPTION2_REG, ®50);
895 pci_write_config_dword(minfo->pcidev, PCI_OPTION2_REG, reg50);
898 pci_write_config_dword(minfo->pcidev, PCI_OPTION_REG, hw->MXoptionReg);
899 mga_outl(M_CTLWTST, minfo->values.reg.mctlwtst);
909 pci_write_config_dword(minfo->pcidev, PCI_OPTION2_REG, reg50);
915 mga_writeb(minfo->video.vbase, 0x0000, 0xAA);
916 mga_writeb(minfo->video.vbase, 0x0800, 0x55);
917 mga_writeb(minfo->video.vbase, 0x4000, 0x55);
919 } else if (minfo->devflags.accelerator == FB_ACCEL_MATROX_MGAG200) {
920 pci_read_config_dword(minfo->pcidev, PCI_OPTION2_REG, ®50);
922 pci_write_config_dword(minfo->pcidev, PCI_OPTION2_REG, reg50);
924 if (minfo->devflags.memtype == -1)
925 hw->MXoptionReg |= minfo->values.reg.opt & 0x1C00;
927 hw->MXoptionReg |= (minfo->devflags.memtype & 7) << 10;
928 if (minfo->devflags.sgram)
930 mga_outl(M_CTLWTST, minfo->values.reg.mctlwtst);
931 mga_outl(M_MEMRDBK, minfo->values.reg.memrdbk);
936 mga_outw(M_MEMRDBK, minfo->values.reg.memrdbk);
939 pci_read_config_dword(minfo->pcidev, PCI_OPTION2_REG, ®50);
942 pci_write_config_dword(minfo->pcidev, PCI_OPTION2_REG, reg50);
944 if (minfo->devflags.memtype == -1)
945 hw->MXoptionReg |= minfo->values.reg.opt & 0x1C00;
947 hw->MXoptionReg |= (minfo->devflags.memtype & 7) << 10;
948 if (minfo->devflags.sgram)
950 mga_outl(M_CTLWTST, minfo->values.reg.mctlwtst);
951 mga_outl(M_MEMRDBK, minfo->values.reg.memrdbk);
956 mga_outl(M_MEMRDBK, minfo->values.reg.memrdbk);
959 pci_write_config_dword(minfo->pcidev, PCI_OPTION_REG, hw->MXoptionReg);
963 static void MGAG100_reset(struct matrox_fb_info *minfo)
966 struct matrox_hw_state *hw = &minfo->hw;
976 if (b == minfo->pcidev->bus->number) {
983 if (!minfo->devflags.noinit) {
986 pci_write_config_dword(minfo->pcidev, PCI_OPTION_REG, hw->MXoptionReg);
991 if (minfo->devflags.g450dac) {
993 hw->DACclk[3] = inDAC1064(minfo, DAC1064_XSYSPLLM);
994 hw->DACclk[4] = inDAC1064(minfo, DAC1064_XSYSPLLN);
995 hw->DACclk[5] = inDAC1064(minfo, DAC1064_XSYSPLLP);
997 DAC1064_setmclk(minfo, DAC1064_OPT_RESERVED | DAC1064_OPT_MDIV2 | DAC1064_OPT_GDIV1 | DAC1064_OPT_SCLK_PLL, 133333);
999 if (minfo->devflags.accelerator == FB_ACCEL_MATROX_MGAG400) {
1000 if (minfo->devflags.dfp_type == -1) {
1001 minfo->devflags.dfp_type = inDAC1064(minfo, 0x1F);
1004 if (minfo->devflags.noinit)
1006 if (minfo->devflags.g450dac) {
1008 MGAG100_setPixClock(minfo, 4, 25175);
1009 MGAG100_setPixClock(minfo, 5, 28322);
1011 b = inDAC1064(minfo, M1064_XGENIODATA) & ~1;
1012 outDAC1064(minfo, M1064_XGENIODATA, b);
1013 b = inDAC1064(minfo, M1064_XGENIOCTRL) | 1;
1014 outDAC1064(minfo, M1064_XGENIOCTRL, b);
1021 static void MGA1064_restore(struct matrox_fb_info *minfo)
1024 struct matrox_hw_state *hw = &minfo->hw;
1032 pci_write_config_dword(minfo->pcidev, PCI_OPTION_REG, hw->MXoptionReg);
1038 DAC1064_restore_1(minfo);
1039 matroxfb_vgaHWrestore(minfo);
1040 minfo->crtc1.panpos = -1;
1043 DAC1064_restore_2(minfo);
1048 static void MGAG100_restore(struct matrox_fb_info *minfo)
1051 struct matrox_hw_state *hw = &minfo->hw;
1059 pci_write_config_dword(minfo->pcidev, PCI_OPTION_REG, hw->MXoptionReg);
1062 DAC1064_restore_1(minfo);
1063 matroxfb_vgaHWrestore(minfo);
1064 if (minfo->devflags.support32MB)
1066 minfo->crtc1.panpos = -1;
1069 DAC1064_restore_2(minfo);