Lines Matching refs:hw
472 int intelfbhw_active_pipe(const struct intelfb_hwstate *hw)
477 if (hw->disp_b_ctrl & DISPPLANE_PLANE_ENABLE) {
478 pipe = (hw->disp_b_ctrl >> DISPPLANE_SEL_PIPE_SHIFT);
483 if (hw->disp_a_ctrl & DISPPLANE_PLANE_ENABLE) {
484 pipe = (hw->disp_a_ctrl >> DISPPLANE_SEL_PIPE_SHIFT);
517 struct intelfb_hwstate *hw, int flag)
525 if (!hw || !dinfo)
529 hw->vga0_divisor = INREG(VGA0_DIVISOR);
530 hw->vga1_divisor = INREG(VGA1_DIVISOR);
531 hw->vga_pd = INREG(VGAPD);
532 hw->dpll_a = INREG(DPLL_A);
533 hw->dpll_b = INREG(DPLL_B);
534 hw->fpa0 = INREG(FPA0);
535 hw->fpa1 = INREG(FPA1);
536 hw->fpb0 = INREG(FPB0);
537 hw->fpb1 = INREG(FPB1);
546 hw->htotal_a = INREG(HTOTAL_A);
547 hw->hblank_a = INREG(HBLANK_A);
548 hw->hsync_a = INREG(HSYNC_A);
549 hw->vtotal_a = INREG(VTOTAL_A);
550 hw->vblank_a = INREG(VBLANK_A);
551 hw->vsync_a = INREG(VSYNC_A);
552 hw->src_size_a = INREG(SRC_SIZE_A);
553 hw->bclrpat_a = INREG(BCLRPAT_A);
554 hw->htotal_b = INREG(HTOTAL_B);
555 hw->hblank_b = INREG(HBLANK_B);
556 hw->hsync_b = INREG(HSYNC_B);
557 hw->vtotal_b = INREG(VTOTAL_B);
558 hw->vblank_b = INREG(VBLANK_B);
559 hw->vsync_b = INREG(VSYNC_B);
560 hw->src_size_b = INREG(SRC_SIZE_B);
561 hw->bclrpat_b = INREG(BCLRPAT_B);
566 hw->adpa = INREG(ADPA);
567 hw->dvoa = INREG(DVOA);
568 hw->dvob = INREG(DVOB);
569 hw->dvoc = INREG(DVOC);
570 hw->dvoa_srcdim = INREG(DVOA_SRCDIM);
571 hw->dvob_srcdim = INREG(DVOB_SRCDIM);
572 hw->dvoc_srcdim = INREG(DVOC_SRCDIM);
573 hw->lvds = INREG(LVDS);
578 hw->pipe_a_conf = INREG(PIPEACONF);
579 hw->pipe_b_conf = INREG(PIPEBCONF);
580 hw->disp_arb = INREG(DISPARB);
585 hw->cursor_a_control = INREG(CURSOR_A_CONTROL);
586 hw->cursor_b_control = INREG(CURSOR_B_CONTROL);
587 hw->cursor_a_base = INREG(CURSOR_A_BASEADDR);
588 hw->cursor_b_base = INREG(CURSOR_B_BASEADDR);
594 hw->cursor_a_palette[i] = INREG(CURSOR_A_PALETTE0 + (i << 2));
595 hw->cursor_b_palette[i] = INREG(CURSOR_B_PALETTE0 + (i << 2));
601 hw->cursor_size = INREG(CURSOR_SIZE);
606 hw->disp_a_ctrl = INREG(DSPACNTR);
607 hw->disp_b_ctrl = INREG(DSPBCNTR);
608 hw->disp_a_base = INREG(DSPABASE);
609 hw->disp_b_base = INREG(DSPBBASE);
610 hw->disp_a_stride = INREG(DSPASTRIDE);
611 hw->disp_b_stride = INREG(DSPBSTRIDE);
616 hw->vgacntrl = INREG(VGACNTRL);
621 hw->add_id = INREG(ADD_ID);
627 hw->swf0x[i] = INREG(SWF00 + (i << 2));
628 hw->swf1x[i] = INREG(SWF10 + (i << 2));
630 hw->swf3x[i] = INREG(SWF30 + (i << 2));
634 hw->fence[i] = INREG(FENCE + (i << 2));
636 hw->instpm = INREG(INSTPM);
637 hw->mem_mode = INREG(MEM_MODE);
638 hw->fw_blc_0 = INREG(FW_BLC_0);
639 hw->fw_blc_1 = INREG(FW_BLC_1);
641 hw->hwstam = INREG16(HWSTAM);
642 hw->ier = INREG16(IER);
643 hw->iir = INREG16(IIR);
644 hw->imr = INREG16(IMR);
704 struct intelfb_hwstate *hw)
711 if (!hw)
714 printk("hw state dump start\n");
715 printk(" VGA0_DIVISOR: 0x%08x\n", hw->vga0_divisor);
716 printk(" VGA1_DIVISOR: 0x%08x\n", hw->vga1_divisor);
717 printk(" VGAPD: 0x%08x\n", hw->vga_pd);
718 n = (hw->vga0_divisor >> FP_N_DIVISOR_SHIFT) & FP_DIVISOR_MASK;
719 m1 = (hw->vga0_divisor >> FP_M1_DIVISOR_SHIFT) & FP_DIVISOR_MASK;
720 m2 = (hw->vga0_divisor >> FP_M2_DIVISOR_SHIFT) & FP_DIVISOR_MASK;
722 intelfbhw_get_p1p2(dinfo, hw->vga_pd, &p1, &p2);
729 n = (hw->vga1_divisor >> FP_N_DIVISOR_SHIFT) & FP_DIVISOR_MASK;
730 m1 = (hw->vga1_divisor >> FP_M1_DIVISOR_SHIFT) & FP_DIVISOR_MASK;
731 m2 = (hw->vga1_divisor >> FP_M2_DIVISOR_SHIFT) & FP_DIVISOR_MASK;
733 intelfbhw_get_p1p2(dinfo, hw->vga_pd, &p1, &p2);
739 printk(" DPLL_A: 0x%08x\n", hw->dpll_a);
740 printk(" DPLL_B: 0x%08x\n", hw->dpll_b);
741 printk(" FPA0: 0x%08x\n", hw->fpa0);
742 printk(" FPA1: 0x%08x\n", hw->fpa1);
743 printk(" FPB0: 0x%08x\n", hw->fpb0);
744 printk(" FPB1: 0x%08x\n", hw->fpb1);
746 n = (hw->fpa0 >> FP_N_DIVISOR_SHIFT) & FP_DIVISOR_MASK;
747 m1 = (hw->fpa0 >> FP_M1_DIVISOR_SHIFT) & FP_DIVISOR_MASK;
748 m2 = (hw->fpa0 >> FP_M2_DIVISOR_SHIFT) & FP_DIVISOR_MASK;
750 intelfbhw_get_p1p2(dinfo, hw->dpll_a, &p1, &p2);
757 n = (hw->fpa1 >> FP_N_DIVISOR_SHIFT) & FP_DIVISOR_MASK;
758 m1 = (hw->fpa1 >> FP_M1_DIVISOR_SHIFT) & FP_DIVISOR_MASK;
759 m2 = (hw->fpa1 >> FP_M2_DIVISOR_SHIFT) & FP_DIVISOR_MASK;
761 intelfbhw_get_p1p2(dinfo, hw->dpll_a, &p1, &p2);
769 printk(" HTOTAL_A: 0x%08x\n", hw->htotal_a);
770 printk(" HBLANK_A: 0x%08x\n", hw->hblank_a);
771 printk(" HSYNC_A: 0x%08x\n", hw->hsync_a);
772 printk(" VTOTAL_A: 0x%08x\n", hw->vtotal_a);
773 printk(" VBLANK_A: 0x%08x\n", hw->vblank_a);
774 printk(" VSYNC_A: 0x%08x\n", hw->vsync_a);
775 printk(" SRC_SIZE_A: 0x%08x\n", hw->src_size_a);
776 printk(" BCLRPAT_A: 0x%08x\n", hw->bclrpat_a);
777 printk(" HTOTAL_B: 0x%08x\n", hw->htotal_b);
778 printk(" HBLANK_B: 0x%08x\n", hw->hblank_b);
779 printk(" HSYNC_B: 0x%08x\n", hw->hsync_b);
780 printk(" VTOTAL_B: 0x%08x\n", hw->vtotal_b);
781 printk(" VBLANK_B: 0x%08x\n", hw->vblank_b);
782 printk(" VSYNC_B: 0x%08x\n", hw->vsync_b);
783 printk(" SRC_SIZE_B: 0x%08x\n", hw->src_size_b);
784 printk(" BCLRPAT_B: 0x%08x\n", hw->bclrpat_b);
786 printk(" ADPA: 0x%08x\n", hw->adpa);
787 printk(" DVOA: 0x%08x\n", hw->dvoa);
788 printk(" DVOB: 0x%08x\n", hw->dvob);
789 printk(" DVOC: 0x%08x\n", hw->dvoc);
790 printk(" DVOA_SRCDIM: 0x%08x\n", hw->dvoa_srcdim);
791 printk(" DVOB_SRCDIM: 0x%08x\n", hw->dvob_srcdim);
792 printk(" DVOC_SRCDIM: 0x%08x\n", hw->dvoc_srcdim);
793 printk(" LVDS: 0x%08x\n", hw->lvds);
795 printk(" PIPEACONF: 0x%08x\n", hw->pipe_a_conf);
796 printk(" PIPEBCONF: 0x%08x\n", hw->pipe_b_conf);
797 printk(" DISPARB: 0x%08x\n", hw->disp_arb);
799 printk(" CURSOR_A_CONTROL: 0x%08x\n", hw->cursor_a_control);
800 printk(" CURSOR_B_CONTROL: 0x%08x\n", hw->cursor_b_control);
801 printk(" CURSOR_A_BASEADDR: 0x%08x\n", hw->cursor_a_base);
802 printk(" CURSOR_B_BASEADDR: 0x%08x\n", hw->cursor_b_base);
806 printk("0x%08x", hw->cursor_a_palette[i]);
813 printk("0x%08x", hw->cursor_b_palette[i]);
819 printk(" CURSOR_SIZE: 0x%08x\n", hw->cursor_size);
821 printk(" DSPACNTR: 0x%08x\n", hw->disp_a_ctrl);
822 printk(" DSPBCNTR: 0x%08x\n", hw->disp_b_ctrl);
823 printk(" DSPABASE: 0x%08x\n", hw->disp_a_base);
824 printk(" DSPBBASE: 0x%08x\n", hw->disp_b_base);
825 printk(" DSPASTRIDE: 0x%08x\n", hw->disp_a_stride);
826 printk(" DSPBSTRIDE: 0x%08x\n", hw->disp_b_stride);
828 printk(" VGACNTRL: 0x%08x\n", hw->vgacntrl);
829 printk(" ADD_ID: 0x%08x\n", hw->add_id);
833 hw->swf0x[i]);
837 hw->swf1x[i]);
841 hw->swf3x[i]);
845 hw->fence[i]);
847 printk(" INSTPM 0x%08x\n", hw->instpm);
848 printk(" MEM_MODE 0x%08x\n", hw->mem_mode);
849 printk(" FW_BLC_0 0x%08x\n", hw->fw_blc_0);
850 printk(" FW_BLC_1 0x%08x\n", hw->fw_blc_1);
852 printk(" HWSTAM 0x%04x\n", hw->hwstam);
853 printk(" IER 0x%04x\n", hw->ier);
854 printk(" IIR 0x%04x\n", hw->iir);
855 printk(" IMR 0x%04x\n", hw->imr);
856 printk("hw state dump end\n");
1027 /* It is assumed that hw is filled in with the initial state information. */
1029 struct intelfb_hwstate *hw,
1032 int pipe = intelfbhw_active_pipe(hw);
1044 hw->vgacntrl |= VGA_DISABLE;
1048 dpll = &hw->dpll_b;
1049 fp0 = &hw->fpb0;
1050 fp1 = &hw->fpb1;
1051 hs = &hw->hsync_b;
1052 hb = &hw->hblank_b;
1053 ht = &hw->htotal_b;
1054 vs = &hw->vsync_b;
1055 vb = &hw->vblank_b;
1056 vt = &hw->vtotal_b;
1057 ss = &hw->src_size_b;
1058 pipe_conf = &hw->pipe_b_conf;
1060 dpll = &hw->dpll_a;
1061 fp0 = &hw->fpa0;
1062 fp1 = &hw->fpa1;
1063 hs = &hw->hsync_a;
1064 hb = &hw->hblank_a;
1065 ht = &hw->htotal_a;
1066 vs = &hw->vsync_a;
1067 vb = &hw->vblank_a;
1068 vt = &hw->vtotal_a;
1069 ss = &hw->src_size_a;
1070 pipe_conf = &hw->pipe_a_conf;
1074 hw->adpa &= ~ADPA_USE_VGA_HVPOLARITY;
1081 hw->adpa &= ~((ADPA_SYNC_ACTIVE_MASK << ADPA_VSYNC_ACTIVE_SHIFT) |
1083 hw->adpa |= (hsync_pol << ADPA_HSYNC_ACTIVE_SHIFT) |
1087 hw->adpa &= ~(PIPE_MASK << ADPA_PIPE_SELECT_SHIFT);
1088 hw->adpa |= (pipe << ADPA_PIPE_SELECT_SHIFT);
1091 hw->adpa &= ~ADPA_DPMS_CONTROL_MASK;
1092 hw->adpa |= ADPA_DPMS_D0;
1094 hw->adpa |= ADPA_DAC_ENABLE;
1136 hw->dvob &= ~PORT_ENABLE;
1137 hw->dvoc &= ~PORT_ENABLE;
1140 hw->disp_a_ctrl |= DISPPLANE_PLANE_ENABLE;
1141 hw->disp_a_ctrl &= ~DISPPLANE_GAMMA_ENABLE;
1142 hw->disp_a_ctrl &= ~DISPPLANE_PIXFORMAT_MASK;
1145 hw->disp_a_ctrl |= DISPPLANE_8BPP | DISPPLANE_GAMMA_ENABLE;
1148 hw->disp_a_ctrl |= DISPPLANE_15_16BPP;
1151 hw->disp_a_ctrl |= DISPPLANE_16BPP;
1154 hw->disp_a_ctrl |= DISPPLANE_32BPP_NO_ALPHA;
1157 hw->disp_a_ctrl &= ~(PIPE_MASK << DISPPLANE_SEL_PIPE_SHIFT);
1158 hw->disp_a_ctrl |= (pipe << DISPPLANE_SEL_PIPE_SHIFT);
1237 hw->disp_a_stride = dinfo->pitch;
1238 DBG_MSG("pitch is %d\n", hw->disp_a_stride);
1240 hw->disp_a_base = hw->disp_a_stride * var->yoffset +
1243 hw->disp_a_base += dinfo->fb.offset << 12;
1248 if (hw->disp_a_stride % stride_alignment != 0) {
1250 hw->disp_a_stride, stride_alignment);
1267 const struct intelfb_hwstate *hw, int blank)
1289 dinfo->pipe = intelfbhw_active_pipe(hw);
1292 dpll = &hw->dpll_b;
1293 fp0 = &hw->fpb0;
1294 fp1 = &hw->fpb1;
1295 pipe_conf = &hw->pipe_b_conf;
1296 hs = &hw->hsync_b;
1297 hb = &hw->hblank_b;
1298 ht = &hw->htotal_b;
1299 vs = &hw->vsync_b;
1300 vb = &hw->vblank_b;
1301 vt = &hw->vtotal_b;
1302 ss = &hw->src_size_b;
1316 dpll = &hw->dpll_a;
1317 fp0 = &hw->fpa0;
1318 fp1 = &hw->fpa1;
1319 pipe_conf = &hw->pipe_a_conf;
1320 hs = &hw->hsync_a;
1321 hb = &hw->hblank_a;
1322 ht = &hw->htotal_a;
1323 vs = &hw->vsync_a;
1324 vb = &hw->vblank_a;
1325 vt = &hw->vtotal_a;
1326 ss = &hw->src_size_a;
1399 OUTREG(DVOB, hw->dvob);
1400 OUTREG(DVOC, hw->dvoc);
1407 OUTREG(ADPA, (hw->adpa & ~(ADPA_DPMS_CONTROL_MASK)) | ADPA_DPMS_D3);
1450 hw->disp_a_ctrl|DISPPLANE_PLANE_ENABLE);
1455 OUTREG(DSPACNTR, hw->disp_a_ctrl & ~DISPPLANE_PLANE_ENABLE);
1456 OUTREG(DSPASTRIDE, hw->disp_a_stride);
1457 OUTREG(DSPABASE, hw->disp_a_base);
1464 OUTREG(DSPABASE, hw->disp_a_base);