Lines Matching refs:p1
657 static int calc_vclock(int index, int m1, int m2, int n, int p1, int p2,
668 p = ((p1 + 2) * (1 << (p2 + 1)));
670 p = ((p1) * (p2 ? 5 : 10));
678 int p1, p2;
682 p1 = 1;
684 p1 = (dpll >> DPLL_P1_SHIFT) & 0xff;
686 p1 = ffs(p1);
691 p1 = 0;
693 p1 = (dpll >> DPLL_P1_SHIFT) & DPLL_P1_MASK;
697 *o_p1 = p1;
707 int i, m1, m2, n, p1, p2;
722 intelfbhw_get_p1p2(dinfo, hw->vga_pd, &p1, &p2);
724 printk(" VGA0: (m1, m2, n, p1, p2) = (%d, %d, %d, %d, %d)\n",
725 m1, m2, n, p1, p2);
727 calc_vclock(index, m1, m2, n, p1, p2, 0));
733 intelfbhw_get_p1p2(dinfo, hw->vga_pd, &p1, &p2);
734 printk(" VGA1: (m1, m2, n, p1, p2) = (%d, %d, %d, %d, %d)\n",
735 m1, m2, n, p1, p2);
737 calc_vclock(index, m1, m2, n, p1, p2, 0));
750 intelfbhw_get_p1p2(dinfo, hw->dpll_a, &p1, &p2);
752 printk(" PLLA0: (m1, m2, n, p1, p2) = (%d, %d, %d, %d, %d)\n",
753 m1, m2, n, p1, p2);
755 calc_vclock(index, m1, m2, n, p1, p2, 0));
761 intelfbhw_get_p1p2(dinfo, hw->dpll_a, &p1, &p2);
763 printk(" PLLA1: (m1, m2, n, p1, p2) = (%d, %d, %d, %d, %d)\n",
764 m1, m2, n, p1, p2);
766 calc_vclock(index, m1, m2, n, p1, p2, 0));
888 int p1, p2;
894 p1 = p / (p2 ? 5 : 10);
896 *retp1 = (unsigned int)p1;
905 p1 = (p / (1 << (p2 + 1))) - 2;
906 if (p % 4 == 0 && p1 < pll->min_p1) {
908 p1 = (p / (1 << (p2 + 1))) - 2;
910 if (p1 < pll->min_p1 || p1 > pll->max_p1 ||
911 (p1 + 2) * (1 << (p2 + 1)) != p) {
914 *retp1 = (unsigned int)p1;
923 u32 m1, m2, n, p1, p2, n1, testm;
950 if (splitp(index, p, &p1, &p2)) {
997 splitp(index, p, &p1, &p2);
1002 m, m1, m2, n, n1, p, p1, p2,
1004 calc_vclock(index, m1, m2, n1, p1, p2, 0),
1009 *retp1 = p1;
1011 *retclock = calc_vclock(index, m1, m2, n1, p1, p2, 0);
1034 u32 m1, m2, n, p1, p2, clock_target, clock;
1104 &n, &p1, &p2, &clock)) {
1110 if (check_overflow(p1, DPLL_P1_MASK, "PLL P1 parameter"))
1127 *dpll |= (1 << (p1 - 1)) << DPLL_P1_SHIFT;
1129 *dpll |= (p2 << DPLL_P2_SHIFT) | (p1 << DPLL_P1_SHIFT);