Lines Matching defs:m2
657 static int calc_vclock(int index, int m1, int m2, int n, int p1, int p2,
663 m = (5 * (m1 + 2)) + (m2 + 2);
707 int i, m1, m2, n, p1, p2;
720 m2 = (hw->vga0_divisor >> FP_M2_DIVISOR_SHIFT) & FP_DIVISOR_MASK;
724 printk(" VGA0: (m1, m2, n, p1, p2) = (%d, %d, %d, %d, %d)\n",
725 m1, m2, n, p1, p2);
727 calc_vclock(index, m1, m2, n, p1, p2, 0));
731 m2 = (hw->vga1_divisor >> FP_M2_DIVISOR_SHIFT) & FP_DIVISOR_MASK;
734 printk(" VGA1: (m1, m2, n, p1, p2) = (%d, %d, %d, %d, %d)\n",
735 m1, m2, n, p1, p2);
737 calc_vclock(index, m1, m2, n, p1, p2, 0));
748 m2 = (hw->fpa0 >> FP_M2_DIVISOR_SHIFT) & FP_DIVISOR_MASK;
752 printk(" PLLA0: (m1, m2, n, p1, p2) = (%d, %d, %d, %d, %d)\n",
753 m1, m2, n, p1, p2);
755 calc_vclock(index, m1, m2, n, p1, p2, 0));
759 m2 = (hw->fpa1 >> FP_M2_DIVISOR_SHIFT) & FP_DIVISOR_MASK;
763 printk(" PLLA1: (m1, m2, n, p1, p2) = (%d, %d, %d, %d, %d)\n",
764 m1, m2, n, p1, p2);
766 calc_vclock(index, m1, m2, n, p1, p2, 0));
866 int m1, m2;
872 for (m2 = pll->min_m2; m2 < pll->max_m2 + 1; m2++) {
873 testm = (5 * (m1 + 2)) + (m2 + 2);
876 *retm2 = (unsigned int)m2;
923 u32 m1, m2, n, p1, p2, n1, testm;
966 if (splitm(index, testm, &m1, &m2)) {
996 splitm(index, m, &m1, &m2);
1002 m, m1, m2, n, n1, p, p1, p2,
1004 calc_vclock(index, m1, m2, n1, p1, p2, 0),
1007 *retm2 = m2;
1011 *retclock = calc_vclock(index, m1, m2, n1, p1, p2, 0);
1034 u32 m1, m2, n, p1, p2, clock_target, clock;
1103 if (calc_pll_params(dinfo->pll_index, clock_target, &m1, &m2,
1116 if (check_overflow(m2, FP_DIVISOR_MASK, "PLL M2 parameter"))
1133 (m2 << FP_M2_DIVISOR_SHIFT);