Lines Matching refs:dc_regs
89 readl(par->dc_regs + DC_UNLOCK);
90 writel(DC_UNLOCK_CODE, par->dc_regs + DC_UNLOCK);
92 gcfg = readl(par->dc_regs + DC_GENERAL_CFG);
93 tcfg = readl(par->dc_regs + DC_TIMING_CFG);
97 writel(tcfg, par->dc_regs + DC_TIMING_CFG);
104 writel(gcfg, par->dc_regs + DC_GENERAL_CFG);
108 writel(gcfg, par->dc_regs + DC_GENERAL_CFG);
114 writel(gcfg, par->dc_regs + DC_GENERAL_CFG);
133 writel(0, par->dc_regs + DC_FB_ST_OFFSET);
136 writel(info->fix.line_length >> 2, par->dc_regs + DC_LINE_DELTA);
138 par->dc_regs + DC_BUF_SIZE);
164 writel(val, par->dc_regs + DC_H_TIMING_1);
166 writel(val, par->dc_regs + DC_H_TIMING_2);
168 writel(val, par->dc_regs + DC_H_TIMING_3);
169 writel(val, par->dc_regs + DC_FP_H_TIMING);
171 writel(val, par->dc_regs + DC_V_TIMING_1);
173 writel(val, par->dc_regs + DC_V_TIMING_2);
175 writel(val, par->dc_regs + DC_V_TIMING_3);
177 writel(val, par->dc_regs + DC_FP_V_TIMING);
180 writel(ocfg, par->dc_regs + DC_OUTPUT_CFG);
181 writel(tcfg, par->dc_regs + DC_TIMING_CFG);
183 writel(gcfg, par->dc_regs + DC_GENERAL_CFG);
188 writel(0, par->dc_regs + DC_UNLOCK);
203 writel(regno, par->dc_regs + DC_PAL_ADDRESS);
204 writel(val, par->dc_regs + DC_PAL_DATA);