Lines Matching defs:Data
586 __u16 Data;
659 rv = mos7840_get_reg(mos7840_port, wval, wreg, &Data);
877 __u16 Data;
942 Data = 0x0;
943 status = mos7840_get_reg_sync(port, mos7840_port->SpRegOffset, &Data);
948 Data |= 0x80;
949 status = mos7840_set_reg_sync(port, mos7840_port->SpRegOffset, Data);
955 Data &= ~0x80;
956 status = mos7840_set_reg_sync(port, mos7840_port->SpRegOffset, Data);
963 Data = 0x0;
965 &Data);
970 Data |= 0x08; /* Driver done bit */
971 Data |= 0x20; /* rx_disable */
973 mos7840_port->ControlRegOffset, Data);
983 Data = 0x00;
984 status = mos7840_set_uart_reg(port, INTERRUPT_ENABLE_REGISTER, Data);
990 Data = 0x00;
991 status = mos7840_set_uart_reg(port, FIFO_CONTROL_REGISTER, Data);
997 Data = 0xcf;
998 status = mos7840_set_uart_reg(port, FIFO_CONTROL_REGISTER, Data);
1004 Data = 0x03;
1005 status = mos7840_set_uart_reg(port, LINE_CONTROL_REGISTER, Data);
1006 mos7840_port->shadowLCR = Data;
1008 Data = 0x0b;
1009 status = mos7840_set_uart_reg(port, MODEM_CONTROL_REGISTER, Data);
1010 mos7840_port->shadowMCR = Data;
1012 Data = 0x00;
1013 status = mos7840_get_uart_reg(port, LINE_CONTROL_REGISTER, &Data);
1014 mos7840_port->shadowLCR = Data;
1016 Data |= SERIAL_LCR_DLAB; /* data latch enable in LCR 0x80 */
1017 status = mos7840_set_uart_reg(port, LINE_CONTROL_REGISTER, Data);
1019 Data = 0x0c;
1020 status = mos7840_set_uart_reg(port, DIVISOR_LATCH_LSB, Data);
1022 Data = 0x0;
1023 status = mos7840_set_uart_reg(port, DIVISOR_LATCH_MSB, Data);
1025 Data = 0x00;
1026 status = mos7840_get_uart_reg(port, LINE_CONTROL_REGISTER, &Data);
1028 Data = Data & ~SERIAL_LCR_DLAB;
1029 status = mos7840_set_uart_reg(port, LINE_CONTROL_REGISTER, Data);
1030 mos7840_port->shadowLCR = Data;
1033 Data = 0x0;
1034 status = mos7840_get_reg_sync(port, mos7840_port->SpRegOffset, &Data);
1036 Data = Data | 0x0c;
1037 status = mos7840_set_reg_sync(port, mos7840_port->SpRegOffset, Data);
1039 Data = Data & ~0x0c;
1040 status = mos7840_set_reg_sync(port, mos7840_port->SpRegOffset, Data);
1042 Data = 0x0c;
1043 status = mos7840_set_uart_reg(port, INTERRUPT_ENABLE_REGISTER, Data);
1046 Data = 0x0;
1048 &Data);
1049 Data = Data & ~0x20;
1051 Data);
1054 Data = 0x0;
1056 &Data);
1057 Data = Data | 0x10;
1059 Data);
1202 __u16 Data;
1273 Data = 0x0;
1274 mos7840_set_uart_reg(port, MODEM_CONTROL_REGISTER, Data);
1276 Data = 0x00;
1277 mos7840_set_uart_reg(port, INTERRUPT_ENABLE_REGISTER, Data);
1436 /* __u16 Data; */
1444 Data = 0x00;
1445 status = mos7840_get_uart_reg(port, LINE_CONTROL_REGISTER, &Data);
1446 mos7840_port->shadowLCR = Data;
1447 dbg("mos7840_write: LINE_CONTROL_REGISTER is %x", Data);
1451 /* Data = 0x03; */
1452 /* status = mos7840_set_uart_reg(port,LINE_CONTROL_REGISTER,Data); */
1453 /* mos7840_port->shadowLCR=Data;//Need to add later */
1455 Data |= SERIAL_LCR_DLAB; /* data latch enable in LCR 0x80 */
1456 status = mos7840_set_uart_reg(port, LINE_CONTROL_REGISTER, Data);
1458 /* Data = 0x0c; */
1459 /* status = mos7840_set_uart_reg(port,DIVISOR_LATCH_LSB,Data); */
1460 Data = 0x00;
1461 status = mos7840_get_uart_reg(port, DIVISOR_LATCH_LSB, &Data);
1462 dbg("mos7840_write:DLL value is %x", Data);
1464 Data = 0x0;
1465 status = mos7840_get_uart_reg(port, DIVISOR_LATCH_MSB, &Data);
1466 dbg("mos7840_write:DLM value is %x", Data);
1468 Data = Data & ~SERIAL_LCR_DLAB;
1471 status = mos7840_set_uart_reg(port, LINE_CONTROL_REGISTER, Data);
1803 __u16 Data;
1833 Data = 0x2b;
1834 mos7840_port->shadowMCR = Data;
1836 Data);
1846 Data = 0xb;
1847 mos7840_port->shadowMCR = Data;
1849 Data);
1860 Data = 0x0;
1864 &Data);
1869 Data = (Data & 0x8f) | clk_sel_val;
1871 Data);
1883 Data = mos7840_port->shadowLCR | SERIAL_LCR_DLAB;
1884 mos7840_port->shadowLCR = Data;
1885 mos7840_set_uart_reg(port, LINE_CONTROL_REGISTER, Data);
1888 Data = (unsigned char)(divisor & 0xff);
1889 dbg("set_serial_baud Value to write DLL is %x", Data);
1890 mos7840_set_uart_reg(port, DIVISOR_LATCH_LSB, Data);
1892 Data = (unsigned char)((divisor & 0xff00) >> 8);
1893 dbg("set_serial_baud Value to write DLM is %x", Data);
1894 mos7840_set_uart_reg(port, DIVISOR_LATCH_MSB, Data);
1897 Data = mos7840_port->shadowLCR & ~SERIAL_LCR_DLAB;
1898 mos7840_port->shadowLCR = Data;
1899 mos7840_set_uart_reg(port, LINE_CONTROL_REGISTER, Data);
1921 __u16 Data;
2012 Data = 0x00;
2013 mos7840_set_uart_reg(port, INTERRUPT_ENABLE_REGISTER, Data);
2015 Data = 0x00;
2016 mos7840_set_uart_reg(port, FIFO_CONTROL_REGISTER, Data);
2018 Data = 0xcf;
2019 mos7840_set_uart_reg(port, FIFO_CONTROL_REGISTER, Data);
2022 Data = mos7840_port->shadowLCR;
2024 mos7840_set_uart_reg(port, LINE_CONTROL_REGISTER, Data);
2026 Data = 0x00b;
2027 mos7840_port->shadowMCR = Data;
2028 mos7840_set_uart_reg(port, MODEM_CONTROL_REGISTER, Data);
2029 Data = 0x00b;
2030 mos7840_set_uart_reg(port, MODEM_CONTROL_REGISTER, Data);
2043 Data = mos7840_port->shadowMCR;
2044 mos7840_set_uart_reg(port, MODEM_CONTROL_REGISTER, Data);
2059 Data = 0x0c;
2060 mos7840_set_uart_reg(port, INTERRUPT_ENABLE_REGISTER, Data);
2340 __u16 Data;
2414 mos7840_port->ControlRegOffset, &Data);
2420 Data, status);
2421 Data |= 0x08; /* setting driver done bit */
2422 Data |= 0x04; /* sp1_bit to have cts change reflect in
2425 /* Data |= 0x20; //rx_disable bit */
2427 mos7840_port->ControlRegOffset, Data);
2437 Data = 0x01;
2439 (__u16) (mos7840_port->DcrRegOffset + 0), Data);
2446 Data = 0x05;
2448 (__u16) (mos7840_port->DcrRegOffset + 1), Data);
2455 Data = 0x24;
2457 (__u16) (mos7840_port->DcrRegOffset + 2), Data);
2465 Data = 0x0;
2467 CLK_START_VALUE_REGISTER, Data);
2474 Data = 0x20;
2476 CLK_MULTI_REGISTER, Data);
2486 Data = 0x00;
2488 SCRATCH_PAD_REGISTER, Data);
2501 Data = 0xff;
2504 ((__u16)mos7840_port->port_num)), Data);
2516 Data = 0xff;
2519 ((__u16)mos7840_port->port_num) - 0x1), Data);
2545 Data = 0x0f;
2546 status = mos7840_set_reg_sync(serial->port[0], ZLP_REG5, Data);