Lines Matching defs:tbase
38 void __iomem *tbase = musb->ctrl_base;
42 rev = musb_readl(tbase, TUSB_DMA_CTRL_REV) & 0xff;
44 die_id = TUSB_DIDR1_HI_CHIP_REV(musb_readl(tbase,
55 void __iomem *tbase = musb->ctrl_base;
62 TUSB_REV_MAJOR(musb_readl(tbase, TUSB_PRCM_REV)),
63 TUSB_REV_MINOR(musb_readl(tbase, TUSB_PRCM_REV)),
65 TUSB_REV_MAJOR(musb_readl(tbase, TUSB_INT_CTRL_REV)),
66 TUSB_REV_MINOR(musb_readl(tbase, TUSB_INT_CTRL_REV)),
68 TUSB_REV_MAJOR(musb_readl(tbase, TUSB_GPIO_REV)),
69 TUSB_REV_MINOR(musb_readl(tbase, TUSB_GPIO_REV)),
71 TUSB_REV_MAJOR(musb_readl(tbase, TUSB_DMA_CTRL_REV)),
72 TUSB_REV_MINOR(musb_readl(tbase, TUSB_DMA_CTRL_REV)),
74 TUSB_DIDR1_HI_CHIP_REV(musb_readl(tbase, TUSB_DIDR1_HI)),
86 void __iomem *tbase = musb->ctrl_base;
91 phy_otg_ctrl = musb_readl(tbase, TUSB_PHY_OTG_CTRL);
92 phy_otg_ena = musb_readl(tbase, TUSB_PHY_OTG_CTRL_ENABLE);
95 musb_writel(tbase, TUSB_PHY_OTG_CTRL, tmp);
98 musb_writel(tbase, TUSB_PHY_OTG_CTRL_ENABLE, tmp);
100 musb_readl(tbase, TUSB_PHY_OTG_CTRL),
101 musb_readl(tbase, TUSB_PHY_OTG_CTRL_ENABLE));
102 } else if (musb_readl(tbase, TUSB_PHY_OTG_CTRL_ENABLE)
105 musb_writel(tbase, TUSB_PHY_OTG_CTRL, tmp);
107 musb_writel(tbase, TUSB_PHY_OTG_CTRL_ENABLE, tmp);
109 musb_readl(tbase, TUSB_PHY_OTG_CTRL),
110 musb_readl(tbase, TUSB_PHY_OTG_CTRL_ENABLE));
271 void __iomem *tbase = musb->ctrl_base;
298 reg = musb_readl(tbase, TUSB_PRCM_MNGMT);
306 musb_writel(tbase, TUSB_PRCM_MNGMT, reg);
318 void __iomem *tbase = musb->ctrl_base;
321 reg = musb_readl(tbase, TUSB_PRCM_CONF);
332 musb_writel(tbase, TUSB_PRCM_CONF, reg);
344 void __iomem *tbase = musb->ctrl_base;
354 musb_writel(tbase, TUSB_PRCM_WAKEUP_MASK, ~wakeup_enables);
361 reg = musb_readl(tbase, TUSB_PRCM_MNGMT);
371 musb_writel(tbase, TUSB_PRCM_MNGMT, reg);
381 void __iomem *tbase = musb->ctrl_base;
385 otg_stat = musb_readl(tbase, TUSB_DEV_OTG_STAT);
386 prcm_mngmt = musb_readl(tbase, TUSB_PRCM_MNGMT);
395 musb_writel(tbase, TUSB_PRCM_MNGMT, tmp);
396 otg_stat = musb_readl(tbase, TUSB_DEV_OTG_STAT);
397 musb_writel(tbase, TUSB_PRCM_MNGMT, prcm_mngmt);
511 void __iomem *tbase = musb->ctrl_base;
520 prcm = musb_readl(tbase, TUSB_PRCM_MNGMT);
521 conf = musb_readl(tbase, TUSB_DEV_CONF);
540 otg_stat = musb_readl(tbase, TUSB_DEV_OTG_STAT);
570 musb_writel(tbase, TUSB_PRCM_MNGMT, prcm);
571 musb_writel(tbase, TUSB_DEV_OTG_TIMER, timer);
572 musb_writel(tbase, TUSB_DEV_CONF, conf);
578 musb_readl(tbase, TUSB_DEV_OTG_STAT),
595 void __iomem *tbase = musb->ctrl_base;
603 otg_stat = musb_readl(tbase, TUSB_DEV_OTG_STAT);
604 phy_otg_ctrl = musb_readl(tbase, TUSB_PHY_OTG_CTRL);
605 phy_otg_ena = musb_readl(tbase, TUSB_PHY_OTG_CTRL_ENABLE);
606 dev_conf = musb_readl(tbase, TUSB_DEV_CONF);
640 musb_writel(tbase, TUSB_PHY_OTG_CTRL,
642 musb_writel(tbase, TUSB_PHY_OTG_CTRL_ENABLE,
644 musb_writel(tbase, TUSB_DEV_CONF, dev_conf);
646 otg_stat = musb_readl(tbase, TUSB_DEV_OTG_STAT);
656 tusb_otg_ints(struct musb *musb, u32 int_src, void __iomem *tbase)
658 u32 otg_stat = musb_readl(tbase, TUSB_DEV_OTG_STAT);
804 void __iomem *tbase = musb->ctrl_base;
811 int_mask = musb_readl(tbase, TUSB_INT_MASK);
812 musb_writel(tbase, TUSB_INT_MASK, ~TUSB_INT_MASK_RESERVED_BITS);
814 int_src = musb_readl(tbase, TUSB_INT_SRC) & ~TUSB_INT_SRC_RESERVED_BITS;
830 musb_writel(tbase, TUSB_SCRATCH_PAD, 0);
831 musb_writel(tbase, TUSB_SCRATCH_PAD, i);
832 reg = musb_readl(tbase, TUSB_SCRATCH_PAD);
840 reg = musb_readl(tbase, TUSB_PRCM_WAKEUP_SOURCE);
841 musb_writel(tbase, TUSB_PRCM_WAKEUP_CLEAR, reg);
859 idle_timeout = tusb_otg_ints(musb, int_src, tbase);
865 u32 dma_src = musb_readl(tbase, TUSB_DMA_INT_SRC);
866 u32 real_dma_src = musb_readl(tbase, TUSB_DMA_INT_MASK);
881 musb_writel(tbase, TUSB_DMA_INT_CLEAR, dma_src);
886 u32 musb_src = musb_readl(tbase, TUSB_USBIP_INT_SRC);
888 musb_writel(tbase, TUSB_USBIP_INT_CLEAR, musb_src);
900 musb_writel(tbase, TUSB_INT_SRC_CLEAR,
905 musb_writel(tbase, TUSB_INT_MASK, int_mask);
920 void __iomem *tbase = musb->ctrl_base;
924 musb_writel(tbase, TUSB_INT_MASK, TUSB_INT_SRC_USB_IP_SOF);
927 musb_writel(tbase, TUSB_USBIP_INT_MASK, 0);
928 musb_writel(tbase, TUSB_DMA_INT_MASK, 0x7fffffff);
929 musb_writel(tbase, TUSB_GPIO_INT_MASK, 0x1ff);
932 musb_writel(tbase, TUSB_USBIP_INT_CLEAR, 0x7fffffff);
933 musb_writel(tbase, TUSB_DMA_INT_CLEAR, 0x7fffffff);
934 musb_writel(tbase, TUSB_GPIO_INT_CLEAR, 0x1ff);
937 musb_writel(tbase, TUSB_INT_SRC_CLEAR, ~TUSB_INT_MASK_RESERVED_BITS);
941 musb_writel(tbase, TUSB_INT_CTRL_CONF,
947 if (!(musb_readl(tbase, TUSB_DEV_OTG_STAT)
949 musb_writel(tbase, TUSB_INT_SRC_SET,
964 void __iomem *tbase = musb->ctrl_base;
968 musb_writel(tbase, TUSB_INT_MASK, ~TUSB_INT_MASK_RESERVED_BITS);
969 musb_writel(tbase, TUSB_USBIP_INT_MASK, 0x7fffffff);
970 musb_writel(tbase, TUSB_DMA_INT_MASK, 0x7fffffff);
971 musb_writel(tbase, TUSB_GPIO_INT_MASK, 0x1ff);
988 void __iomem *tbase = musb->ctrl_base;
994 musb_writel(tbase, TUSB_PULLUP_1_CTRL, 0x0000003F);
997 musb_writel(tbase, TUSB_PULLUP_2_CTRL, 0x01FFFFFF);
1000 musb_writel(tbase, TUSB_GPIO_CONF, TUSB_GPIO_CONF_DMAREQ(0x3f));
1004 musb_writel(tbase, TUSB_DMA_REQ_CONF,
1010 musb_writel(tbase, TUSB_WAIT_COUNT, 1);
1015 void __iomem *tbase = musb->ctrl_base;
1029 if (musb_readl(tbase, TUSB_PROD_TEST_RESET) !=
1044 musb_writel(tbase, TUSB_VLYNQ_CTRL, 8);
1052 musb_writel(tbase, TUSB_PRCM_MNGMT,
1061 reg = musb_readl(tbase, TUSB_PHY_OTG_CTRL_ENABLE);
1063 musb_writel(tbase, TUSB_PHY_OTG_CTRL_ENABLE, reg);
1065 reg = musb_readl(tbase, TUSB_PHY_OTG_CTRL);
1067 musb_writel(tbase, TUSB_PHY_OTG_CTRL, reg);