Lines Matching defs:musb
46 /* ep0 is always musb->endpoints[0].ep_in */
47 #define next_ep0_request(musb) next_in_request(&(musb)->endpoints[0])
77 struct musb *musb,
80 void __iomem *mbase = musb->mregs;
89 result[0] = musb->is_self_powered << USB_DEVICE_SELF_POWERED;
90 result[0] |= musb->may_wakeup << USB_DEVICE_REMOTE_WAKEUP;
92 if (musb->g.is_otg) {
93 result[0] |= musb->g.b_hnp_enable
95 result[0] |= musb->g.a_alt_hnp_support
97 result[0] |= musb->g.a_hnp_support
122 ep = &musb->endpoints[epnum].ep_in;
124 ep = &musb->endpoints[epnum].ep_out;
126 regs = musb->endpoints[epnum].regs;
157 musb_write_fifo(&musb->endpoints[0], len, result);
175 service_in_request(struct musb *musb, const struct usb_ctrlrequest *ctrlrequest)
183 handled = service_tx_status_request(musb,
199 static void musb_g_ep0_giveback(struct musb *musb, struct usb_request *req)
201 musb_g_giveback(&musb->endpoints[0].ep_in, req, 0);
207 static inline void musb_try_b_hnp_enable(struct musb *musb)
209 void __iomem *mbase = musb->mregs;
228 service_zero_data_request(struct musb *musb,
230 __releases(musb->lock)
231 __acquires(musb->lock)
234 void __iomem *mbase = musb->mregs;
243 musb->set_address = true;
244 musb->address = (u8) (ctrlrequest->wValue & 0x7f);
254 musb->may_wakeup = 0;
273 ep = musb->endpoints + epnum;
311 musb_ep_restart(musb, request);
330 musb->may_wakeup = 1;
333 if (musb->g.speed != USB_SPEED_HIGH)
342 musb->test_mode_nr =
348 musb->test_mode_nr =
354 musb->test_mode_nr =
360 musb->test_mode_nr =
367 musb->test_mode_nr =
373 musb->test_mode_nr =
379 musb->test_mode_nr =
385 musb->test_mode_nr =
394 musb->test_mode = true;
398 if (!musb->g.is_otg)
400 musb->g.b_hnp_enable = 1;
401 musb_try_b_hnp_enable(musb);
404 if (!musb->g.is_otg)
406 musb->g.a_hnp_support = 1;
409 if (!musb->g.is_otg)
411 musb->g.a_alt_hnp_support = 1;
440 ep = musb->endpoints + epnum;
491 static void ep0_rxstate(struct musb *musb)
493 void __iomem *regs = musb->control_ep->regs;
497 req = next_ep0_request(musb);
512 musb_read_fifo(&musb->endpoints[0], count, buf);
516 musb->ep0_state = MUSB_EP0_STAGE_STATUSIN;
528 musb->ackpend = csr;
529 musb_g_ep0_giveback(musb, req);
530 if (!musb->ackpend)
532 musb->ackpend = 0;
534 musb_ep_select(musb->mregs, 0);
544 static void ep0_txstate(struct musb *musb)
546 void __iomem *regs = musb->control_ep->regs;
547 struct usb_request *request = next_ep0_request(musb);
562 musb_write_fifo(&musb->endpoints[0], fifo_count, fifo_src);
569 musb->ep0_state = MUSB_EP0_STAGE_STATUSOUT;
580 musb->ackpend = csr;
581 musb_g_ep0_giveback(musb, request);
582 if (!musb->ackpend)
584 musb->ackpend = 0;
588 musb_ep_select(musb->mregs, 0);
599 musb_read_setup(struct musb *musb, struct usb_ctrlrequest *req)
602 void __iomem *regs = musb->control_ep->regs;
604 musb_read_fifo(&musb->endpoints[0], sizeof *req, (u8 *)req);
617 r = next_ep0_request(musb);
619 musb_g_ep0_giveback(musb, r);
629 musb->set_address = false;
630 musb->ackpend = MUSB_CSR0_P_SVDRXPKTRDY;
633 musb->ackpend |= MUSB_CSR0_TXPKTRDY;
634 musb->ep0_state = MUSB_EP0_STAGE_ACKWAIT;
636 musb->ep0_state = MUSB_EP0_STAGE_TX;
641 musb->ackpend = 0;
643 musb->ep0_state = MUSB_EP0_STAGE_RX;
647 forward_to_driver(struct musb *musb, const struct usb_ctrlrequest *ctrlrequest)
648 __releases(musb->lock)
649 __acquires(musb->lock)
652 if (!musb->gadget_driver)
654 spin_unlock(&musb->lock);
655 retval = musb->gadget_driver->setup(&musb->g, ctrlrequest);
656 spin_lock(&musb->lock);
665 irqreturn_t musb_g_ep0_irq(struct musb *musb)
669 void __iomem *mbase = musb->mregs;
670 void __iomem *regs = musb->endpoints[0].regs;
680 decode_ep0stage(musb->ep0_state));
687 musb->ep0_state = MUSB_EP0_STAGE_IDLE;
696 switch (musb->ep0_state) {
698 musb->ep0_state = MUSB_EP0_STAGE_STATUSOUT;
701 musb->ep0_state = MUSB_EP0_STAGE_STATUSIN;
705 decode_ep0stage(musb->ep0_state));
715 switch (musb->ep0_state) {
720 ep0_txstate(musb);
728 ep0_rxstate(musb);
741 if (musb->set_address) {
742 musb->set_address = false;
743 musb_writeb(mbase, MUSB_FADDR, musb->address);
747 else if (musb->test_mode) {
750 if (MUSB_TEST_PACKET == musb->test_mode_nr)
751 musb_load_testpacket(musb);
754 musb->test_mode_nr);
763 req = next_ep0_request(musb);
765 musb_g_ep0_giveback(musb, req);
776 musb->ep0_state = MUSB_EP0_STAGE_IDLE;
787 musb->ep0_state = MUSB_EP0_STAGE_SETUP;
800 musb_read_setup(musb, &setup);
804 if (unlikely(musb->g.speed == USB_SPEED_UNKNOWN)) {
811 musb->g.speed = (power & MUSB_POWER_HSMODE)
816 switch (musb->ep0_state) {
825 musb, &setup);
833 musb->ackpend |= MUSB_CSR0_P_DATAEND;
837 musb->ep0_state =
846 handled = service_in_request(musb, &setup);
848 musb->ackpend = MUSB_CSR0_TXPKTRDY
850 musb->ep0_state =
862 decode_ep0stage(musb->ep0_state));
873 handled = forward_to_driver(musb, &setup);
878 musb->ackpend |= MUSB_CSR0_P_SENDSTALL;
879 musb->ep0_state = MUSB_EP0_STAGE_IDLE;
882 musb->ackpend);
883 musb->ackpend = 0;
899 musb->ep0_state = MUSB_EP0_STAGE_IDLE;
925 struct musb *musb;
934 musb = ep->musb;
935 regs = musb->control_ep->regs;
938 req->musb = musb;
943 spin_lock_irqsave(&musb->lock, lockflags);
950 switch (musb->ep0_state) {
958 musb->ep0_state);
970 musb_ep_select(musb->mregs, 0);
973 if (musb->ep0_state == MUSB_EP0_STAGE_TX)
974 ep0_txstate(musb);
977 else if (musb->ep0_state == MUSB_EP0_STAGE_ACKWAIT) {
981 musb->ep0_state = MUSB_EP0_STAGE_STATUSIN;
983 musb->ackpend | MUSB_CSR0_P_DATAEND);
984 musb->ackpend = 0;
985 musb_g_ep0_giveback(ep->musb, r);
992 } else if (musb->ackpend) {
993 musb_writew(regs, MUSB_CSR0, musb->ackpend);
994 musb->ackpend = 0;
998 spin_unlock_irqrestore(&musb->lock, lockflags);
1011 struct musb *musb;
1021 musb = ep->musb;
1022 base = musb->mregs;
1023 regs = musb->control_ep->regs;
1026 spin_lock_irqsave(&musb->lock, flags);
1034 csr = musb->ackpend;
1036 switch (musb->ep0_state) {
1055 musb->ep0_state = MUSB_EP0_STAGE_IDLE;
1056 musb->ackpend = 0;
1059 DBG(1, "ep0 can't halt in state %d\n", musb->ep0_state);
1064 spin_unlock_irqrestore(&musb->lock, flags);