Lines Matching defs:musb
86 void musb_platform_enable(struct musb *musb)
90 tmp = (musb->epmask & DAVINCI_USB_TX_ENDPTS_MASK)
92 musb_writel(musb->ctrl_base, DAVINCI_USB_INT_MASK_SET_REG, tmp);
94 tmp = (musb->epmask & (0xfffe & DAVINCI_USB_RX_ENDPTS_MASK))
96 musb_writel(musb->ctrl_base, DAVINCI_USB_INT_MASK_SET_REG, tmp);
101 musb_writel(musb->ctrl_base, DAVINCI_USB_INT_MASK_SET_REG, tmp);
110 if (is_otg_enabled(musb))
111 musb_writel(musb->ctrl_base, DAVINCI_USB_INT_SET_REG,
118 void musb_platform_disable(struct musb *musb)
120 musb_writel(musb->ctrl_base, DAVINCI_USB_INT_MASK_CLR_REG,
124 musb_writeb(musb->mregs, MUSB_DEVCTL, 0);
125 musb_writel(musb->ctrl_base, DAVINCI_USB_EOI_REG, 0);
164 static void davinci_source_power(struct musb *musb, int is_on, int immediate)
187 static void davinci_set_vbus(struct musb *musb, int is_on)
189 WARN_ON(is_on && is_peripheral_active(musb));
190 davinci_source_power(musb, is_on, 0);
200 struct musb *musb = (void *)_musb;
201 void __iomem *mregs = musb->mregs;
209 DBG(7, "poll devctl %02x (%s)\n", devctl, otg_state_string(musb));
211 spin_lock_irqsave(&musb->lock, flags);
212 switch (musb->xceiv->state) {
223 musb->xceiv->state = OTG_STATE_A_WAIT_VRISE;
224 musb_writel(musb->ctrl_base, DAVINCI_USB_INT_SET_REG,
228 if (!is_peripheral_enabled(musb))
237 musb->xceiv->state = OTG_STATE_A_IDLE;
242 spin_unlock_irqrestore(&musb->lock, flags);
249 struct musb *musb = __hci;
250 void __iomem *tibase = musb->ctrl_base;
254 spin_lock_irqsave(&musb->lock, flags);
268 cppi = container_of(musb->dma_controller, struct cppi, controller);
269 if (is_cppi_enabled() && musb->dma_controller && !cppi->irq)
277 musb->int_rx = (tmp & DAVINCI_USB_RXINT_MASK)
279 musb->int_tx = (tmp & DAVINCI_USB_TXINT_MASK)
281 musb->int_usb = (tmp & DAVINCI_USB_USBINT_MASK)
293 void __iomem *mregs = musb->mregs;
295 int err = musb->int_usb & MUSB_INTR_VBUSERROR;
297 err = is_host_enabled(musb)
298 && (musb->int_usb & MUSB_INTR_VBUSERROR);
300 musb->int_usb &= ~MUSB_INTR_VBUSERROR;
301 musb->xceiv->state = OTG_STATE_A_WAIT_VFALL;
304 } else if (is_host_enabled(musb) && drvvbus) {
305 MUSB_HST_MODE(musb);
306 musb->xceiv->default_a = 1;
307 musb->xceiv->state = OTG_STATE_A_WAIT_VRISE;
308 portstate(musb->port1_status |= USB_PORT_STAT_POWER);
311 musb->is_active = 0;
312 MUSB_DEV_MODE(musb);
313 musb->xceiv->default_a = 0;
314 musb->xceiv->state = OTG_STATE_B_IDLE;
315 portstate(musb->port1_status &= ~USB_PORT_STAT_POWER);
321 davinci_source_power(musb, drvvbus, 0);
324 otg_state_string(musb),
330 if (musb->int_tx || musb->int_rx || musb->int_usb)
331 retval |= musb_interrupt(musb);
337 if (is_otg_enabled(musb)
338 && musb->xceiv->state == OTG_STATE_B_IDLE)
341 spin_unlock_irqrestore(&musb->lock, flags);
346 int musb_platform_set_mode(struct musb *musb, u8 mode)
352 int __init musb_platform_init(struct musb *musb, void *board_data)
354 void __iomem *tibase = musb->ctrl_base;
358 musb->xceiv = otg_get_transceiver();
359 if (!musb->xceiv)
362 musb->mregs += DAVINCI_BASE_OFFSET;
364 clk_enable(musb->clock);
371 if (is_host_enabled(musb))
372 setup_timer(&otg_workaround, otg_timer, (unsigned long) musb);
374 musb->board_set_vbus = davinci_set_vbus;
375 davinci_source_power(musb, 0, 1);
394 if (is_host_enabled(musb)) {
411 /* NOTE: irqs are in mixed mode, not bypass to pure-musb */
416 musb->isr = davinci_interrupt;
420 clk_disable(musb->clock);
422 otg_put_transceiver(musb->xceiv);
427 int musb_platform_exit(struct musb *musb)
429 if (is_host_enabled(musb))
441 davinci_source_power(musb, 0 /*off*/, 1);
444 if (is_host_enabled(musb) && musb->xceiv->default_a) {
452 devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
471 clk_disable(musb->clock);
473 otg_put_transceiver(musb->xceiv);