Lines Matching defs:tibase
155 void __iomem *tibase;
176 tibase = controller->tibase;
186 tx = tibase + DAVINCI_TXCPPI_STATERAM_OFFSET(i);
196 rx = tibase + DAVINCI_RXCPPI_STATERAM_OFFSET(i);
202 musb_writel(tibase, DAVINCI_TXCPPI_INTENAB_REG,
204 musb_writel(tibase, DAVINCI_RXCPPI_INTENAB_REG,
208 musb_writel(tibase, DAVINCI_TXCPPI_CTRL_REG, DAVINCI_DMA_CTRL_ENABLE);
209 musb_writel(tibase, DAVINCI_RXCPPI_CTRL_REG, DAVINCI_DMA_CTRL_ENABLE);
212 musb_writel(tibase, DAVINCI_RNDIS_REG, 0);
213 musb_writel(tibase, DAVINCI_AUTOREQ_REG, 0);
227 void __iomem *tibase;
232 tibase = controller->tibase;
234 musb_writel(tibase, DAVINCI_TXCPPI_INTCLR_REG,
236 musb_writel(tibase, DAVINCI_RXCPPI_INTCLR_REG,
252 musb_writel(tibase, DAVINCI_TXCPPI_CTRL_REG, DAVINCI_DMA_CTRL_DISABLE);
253 musb_writel(tibase, DAVINCI_RXCPPI_CTRL_REG, DAVINCI_DMA_CTRL_DISABLE);
266 static inline void core_rxirq_disable(void __iomem *tibase, unsigned epnum)
268 musb_writel(tibase, DAVINCI_USB_INT_MASK_CLR_REG, 1 << (epnum + 8));
271 static inline void core_rxirq_enable(void __iomem *tibase, unsigned epnum)
273 musb_writel(tibase, DAVINCI_USB_INT_MASK_SET_REG, 1 << (epnum + 8));
290 void __iomem *tibase;
293 tibase = controller->tibase;
313 core_rxirq_disable(tibase, ep->epnum);
334 void __iomem *tibase;
339 tibase = c->controller->tibase;
343 core_rxirq_enable(tibase, c->index + 1);
364 musb_readl(c->controller->tibase,
411 void __iomem *tibase, int is_rndis)
415 u32 value = musb_readl(tibase, DAVINCI_RNDIS_REG);
424 musb_writel(tibase, DAVINCI_RNDIS_REG, value);
460 void __iomem *tibase, int onepacket, unsigned n_bds)
469 tmp = musb_readl(tibase, DAVINCI_AUTOREQ_REG);
484 musb_writel(tibase, DAVINCI_AUTOREQ_REG, val);
486 tmp = musb_readl(tibase, DAVINCI_AUTOREQ_REG);
763 void __iomem *tibase = musb->ctrl_base;
803 n_bds = cppi_autoreq_update(rx, tibase, onepacket, n_bds);
816 musb_readl(tibase,
894 core_rxirq_enable(tibase, rx->index + 1);
908 i = musb_readl(tibase,
913 musb_writel(tibase,
917 musb_writel(tibase,
921 i = musb_readl(tibase,
927 musb_writel(tibase,
1142 void __iomem *tibase;
1152 tibase = musb->ctrl_base;
1154 tx = musb_readl(tibase, DAVINCI_TXCPPI_MASKED_REG);
1155 rx = musb_readl(tibase, DAVINCI_RXCPPI_MASKED_REG);
1274 core_rxirq_disable(tibase, index + 1);
1280 musb_writel(tibase, DAVINCI_CPPI_EOI_REG, 0);
1302 controller->tibase = mregs - DAVINCI_BASE_OFFSET;
1364 void __iomem *tibase;
1392 tibase = controller->tibase;
1412 value = musb_readl(tibase, DAVINCI_TXCPPI_TEAR_REG);
1414 musb_writel(tibase, DAVINCI_TXCPPI_TEAR_REG, cppi_ch->index);
1452 core_rxirq_disable(tibase, cppi_ch->index + 1);
1456 value = musb_readl(tibase, DAVINCI_AUTOREQ_REG);
1458 musb_writel(tibase, DAVINCI_AUTOREQ_REG, value);